component
TM74HC595
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TM Shenzhen Titan Micro Elec Shifting Register, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+164−8@@ -1,13 +1,174 @@ {+ "schema_version": 1,+ "type": "component", "slug": "tm74hc595",+ "title": "TM74HC595",+ "brief": "TM Shenzhen Titan Micro Elec Shifting Register, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "TM Shenzhen Titan Micro Elec Shifting Register, SOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "tm74hc595" ],+ "component": {+ "mpn": "TM74HC595",+ "manufacturer": "TM Shenzhen Titan Micro Elec",+ "package": "SOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shifting Register",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9a69eb73354ec1d6c6428f1e2e0d0f0f.pdf",+ "parts": {+ "symbol": "tm74hc595.kicad_sym",+ "footprint": "tm74hc595.kicad_mod",+ "model_3d": "tm74hc595.glb",+ "model_3d_step": "tm74hc595.step",+ "lbr": "tm74hc595.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "QB",+ "type": "tri_state",+ "description": "Parallel tri-state output B (bit 2 of the storage register). Drives up to IO = \u00b16.0 mA at VDD = 4.5 V (\u00b17.8 mA at 6.0 V). Placed in high-impedance when /OE is high."+ },+ {+ "number": "2",+ "name": "QC",+ "type": "tri_state",+ "description": "Parallel tri-state output C (bit 3 of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high."+ },+ {+ "number": "3",+ "name": "QD",+ "type": "tri_state",+ "description": "Parallel tri-state output D (bit 4 of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high."+ },+ {+ "number": "4",+ "name": "QE",+ "type": "tri_state",+ "description": "Parallel tri-state output E (bit 5 of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high."+ },+ {+ "number": "5",+ "name": "QF",+ "type": "tri_state",+ "description": "Parallel tri-state output F (bit 6 of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high."+ },+ {+ "number": "6",+ "name": "QG",+ "type": "tri_state",+ "description": "Parallel tri-state output G (bit 7 of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high."+ },+ {+ "number": "7",+ "name": "QH",+ "type": "tri_state",+ "description": "Parallel tri-state output H (bit 8, last stage of the storage register). Same drive characteristics as QA-QH. High-impedance when /OE is high."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground (negative supply) reference for the device. Connect to system 0 V."+ },+ {+ "number": "9",+ "name": "SQH",+ "type": "output",+ "description": "Serial data output - the shifted-out data from the last stage (QH) of the internal shift register. Used to cascade to the SI input of the next TM74HC595 for chains longer than 8 bits. Not tri-stated by /OE."+ },+ {+ "number": "10",+ "name": "SCLR",+ "type": "input",+ "description": "Active-low shift-register clear (/SCLR). Driving this pin low asynchronously resets all stages of the shift register to 0; it does not affect the output storage latches until an RCK rising edge transfers the cleared data."+ },+ {+ "number": "11",+ "name": "SCK",+ "type": "input",+ "description": "Shift-register clock input. Serial data on SI is sampled on the rising edge of SCK and shifted through the internal 8-bit shift register (SPI-compatible). Max frequency > 25 MHz."+ },+ {+ "number": "12",+ "name": "RCK",+ "type": "input",+ "description": "Storage-register (latch) clock input. On the rising edge of RCK, the current contents of the shift register are transferred to the 8-bit output storage latches and appear on QA-QH (subject to /OE)."+ },+ {+ "number": "13",+ "name": "OE",+ "type": "input",+ "description": "Active-low output enable (/OE). When low, QA-QH drive the latched storage-register values; when high, QA-QH go to high impedance. Does not affect SQH or the shift-register contents."+ },+ {+ "number": "14",+ "name": "SI",+ "type": "input",+ "description": "Serial data input. Data present on SI is clocked into the first stage of the shift register on the rising edge of SCK. Setup time tsu \u2248 3.0 ns (VDD=5.0 V), hold time th \u2248 2.0 ns."+ },+ {+ "number": "15",+ "name": "QA",+ "type": "tri_state",+ "description": "Parallel tri-state output A (bit 1, first stage of the storage register). Drives up to IO = \u00b16.0 mA at VDD = 4.5 V (\u00b17.8 mA at 6.0 V). High-impedance when /OE is high."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply input. Recommended operating range 2.0 V to 5.5 V. Quiescent current Icc \u2248 4 \u00b5A (max at 25 \u00b0C, 6 V)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/9a69eb73354ec1d6c6428f1e2e0d0f0f.pdf",+ "pages": 8,+ "sha256": "6212ea9b2c26f3b1",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "TM Shenzhen Titan Micro Elec",+ "Package": "SOP-16",+ "Category": "Logic",+ "Pins": "16"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "tm74hc595"+ ],+ "discovery_pitch": "TM74HC595 (TM Shenzhen Titan Micro Elec) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +186,5 @@ "docs/tm74hc595-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }