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Initial commit: component/tlv62568apdrlt

Ray ·251286ec7b ·9d ago
2 files changed +187
README.mdadded+43
@@ -0,0 +1,43 @@+# TLV62568APDRLT++**Texas Instruments** · DC-DC Converters · SOT-563++TLV62568APDRLT from Texas Instruments, in a SOT-563. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | FB | input | Feedback input pin for the internal control loop connected to an external feedback divider. |+| 2 | GND | power_in | Ground pin. |+| 3 | VIN | power_in | Power supply voltage input, 2.5 V to 5.5 V. |+| 4 | SW | power_out | Switch pin connected to the internal FET switches and external inductor. |+| 5 | EN | input | Device enable logic input; logic high (≥1.2V) enables and logic low (≤0.4V) disables the device. |+| 6 | PG | output | Power good open drain output pin with 0.4 V maximum low voltage at 1 mA sink; pull-up resistor must not exceed 5.5V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOT-563 |+| Category | Power Management (PMIC) |+| Pins | 6 |++## CAD (KiCad official)++- Symbol: `TLV62568APDRLT`+- Footprint: `Package_TO_SOT_SMD:SOT-563`+- 3D model: SOT-563 (KiCad packages3D, STEP)+- 3D model files: `tlv62568apdrlt-etched.step` / `tlv62568apdrlt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv62568apdrlt.step` / `tlv62568apdrlt.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlv62568a) (23 pp, sha256 `60bb6fcb24b14fa4`, retrieved 2026-09-26, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlv62568apdrlt-datasheet.pdf)
page.jsonadded+144
@@ -0,0 +1,144 @@+{+  "slug": "tlv62568apdrlt",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments DC-DC Converters, SOT-563. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "power management (pmic)",+    "tlv62568apdrlt",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "tlv62568apdrlt.kicad_sym",+    "tlv62568apdrlt.kicad_mod",+    "tlv62568apdrlt.glb",+    "tlv62568apdrlt.step",+    "tlv62568apdrlt.lbr",+    "docs/hero.png",+    "docs/tlv62568apdrlt-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "TLV62568APDRLT",+    "manufacturer": "Texas Instruments",+    "package": "SOT-563",+    "pin_count": 6,+    "category": "Power Management (PMIC)",+    "subcategory": "DC-DC Converters",+    "datasheet": "https://www.ti.com/cn/lit/gpn/tlv62568a",+    "parts": {+      "symbol": "tlv62568apdrlt.kicad_sym",+      "footprint": "tlv62568apdrlt.kicad_mod",+      "model_3d": "tlv62568apdrlt-etched.glb",+      "model_3d_plain": "tlv62568apdrlt.glb",+      "model_3d_step": "tlv62568apdrlt-etched.step",+      "model_3d_step_plain": "tlv62568apdrlt.step",+      "lbr": "tlv62568apdrlt.lbr"+    },+    "distributor_links": {+      "lcsc": "C2071896",+      "digikey": "296-49489-2-ND",+      "mouser": "595-TLV62568APDRLT"+    },+    "distributor_check": {+      "checked_at": "2026-09-26T21:14:33Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-49489-2-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "595-TLV62568APDRLT",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "FB",+        "type": "input",+        "description": "Feedback input pin for the internal control loop connected to an external feedback divider."+      },+      {+        "number": "2",+        "name": "GND",+        "type": "power_in",+        "description": "Ground pin."+      },+      {+        "number": "3",+        "name": "VIN",+        "type": "power_in",+        "description": "Power supply voltage input, 2.5 V to 5.5 V."+      },+      {+        "number": "4",+        "name": "SW",+        "type": "power_out",+        "description": "Switch pin connected to the internal FET switches and external inductor."+      },+      {+        "number": "5",+        "name": "EN",+        "type": "input",+        "description": "Device enable logic input; logic high (≥1.2V) enables and logic low (≤0.4V) disables the device."+      },+      {+        "number": "6",+        "name": "PG",+        "type": "output",+        "description": "Power good open drain output pin with 0.4 V maximum low voltage at 1 mA sink; pull-up resistor must not exceed 5.5V."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 23,+        "cost_usd": 0.2484,+        "at": "2026-09-26T21:14:17"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/tlv62568a",+        "pages": 23,+        "sha256": "60bb6fcb24b14fa4",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 6,+        "described": 6,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file