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Initial commit: component/tlv5638cdr

Ray ·15be401a37 ·18d ago
2 files changed +243
README.mdadded+44
@@ -0,0 +1,44 @@+# TLV5638CDR++**Texas Instruments** · Digital To Analog Converters (DAC) · SOIC-8++TLV5638CDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DIN | input | Digital serial data input that receives the 16-bit control and data word, with data setup of 10 ns minimum and hold of 5 ns minimum relative to the SCLK falling edge. |+| 2 | SCLK | input | Digital serial clock input, with a maximum serial clock frequency of 20 MHz and minimum SCLK pulse width high and low of 25 ns each. |+| 3 | CS | input | Active-low chip select that enables the digital inputs, requiring CS low at least 10 ns before the first negative SCLK edge. |+| 4 | OUTA | output | DAC A analog voltage output from the x2 rail-to-rail buffer, specified from 0 V to VDD - 0.4 V at RL = 10 kΩ and driving up to 100 pF load capacitance. |+| 5 | AGND | power_in | Analog ground reference for the device. |+| 6 | REF | bidirectional | Analog reference voltage input or output; as an input it accepts 0 V to VDD - 1.5 V, and as an output the internal reference can source or sink up to 1 mA with a 100 pF load limit. |+| 7 | OUTB | output | DAC B analog voltage output from the x2 rail-to-rail buffer, specified from 0 V to VDD - 0.4 V at RL = 10 kΩ and driving up to 100 pF load capacitance. |+| 8 | VDD | power_in | Positive single-supply input, 2.7 V to 5.5 V recommended with respect to AGND and 7 V absolute maximum. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-8 |+| Category | Data Acquisition |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `TLV5638CDR`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)+- 3D model files: `tlv5638cdr-etched.step` / `tlv5638cdr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv5638cdr.step` / `tlv5638cdr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlv5638) (27 pp, sha256 `5e8282e329ce688a`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlv5638cdr-datasheet.pdf)
page.jsonadded+199
@@ -0,0 +1,199 @@+{+  "slug": "tlv5638cdr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Digital To Analog Converters (DAC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "data acquisition",+    "tlv5638cdr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "tlv5638cdr.kicad_sym",+    "tlv5638cdr.kicad_mod",+    "tlv5638cdr.glb",+    "tlv5638cdr.step",+    "tlv5638cdr.lbr",+    "docs/hero.png",+    "docs/tlv5638cdr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "tlv5638cdr-hero.glb",+    "tlv5638cdr-hero.overlay.json"+  ],+  "component": {+    "mpn": "TLV5638CDR",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "Data Acquisition",+    "subcategory": "Digital To Analog Converters (DAC)",+    "datasheet": "https://www.ti.com/cn/lit/gpn/tlv5638",+    "parts": {+      "symbol": "tlv5638cdr.kicad_sym",+      "footprint": "tlv5638cdr.kicad_mod",+      "model_3d": "tlv5638cdr-hero.glb",+      "model_3d_plain": "tlv5638cdr.glb",+      "model_3d_step": "tlv5638cdr-etched.step",+      "model_3d_step_plain": "tlv5638cdr.step",+      "lbr": "tlv5638cdr.lbr"+    },+    "distributor_links": {+      "lcsc": "C1554719",+      "digikey": "296-41710-2-ND",+      "mouser": "595-TLV5638CDR"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T14:40:54Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-41710-2-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "595-TLV5638CDR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "DIN",+        "type": "input",+        "description": "Digital serial data input that receives the 16-bit control and data word, with data setup of 10 ns minimum and hold of 5 ns minimum relative to the SCLK falling edge."+      },+      {+        "number": "2",+        "name": "SCLK",+        "type": "input",+        "description": "Digital serial clock input, with a maximum serial clock frequency of 20 MHz and minimum SCLK pulse width high and low of 25 ns each."+      },+      {+        "number": "3",+        "name": "CS",+        "type": "input",+        "description": "Active-low chip select that enables the digital inputs, requiring CS low at least 10 ns before the first negative SCLK edge."+      },+      {+        "number": "4",+        "name": "OUTA",+        "type": "output",+        "description": "DAC A analog voltage output from the x2 rail-to-rail buffer, specified from 0 V to VDD - 0.4 V at RL = 10 kΩ and driving up to 100 pF load capacitance."+      },+      {+        "number": "5",+        "name": "AGND",+        "type": "power_in",+        "description": "Analog ground reference for the device."+      },+      {+        "number": "6",+        "name": "REF",+        "type": "bidirectional",+        "description": "Analog reference voltage input or output; as an input it accepts 0 V to VDD - 1.5 V, and as an output the internal reference can source or sink up to 1 mA with a 100 pF load limit."+      },+      {+        "number": "7",+        "name": "OUTB",+        "type": "output",+        "description": "DAC B analog voltage output from the x2 rail-to-rail buffer, specified from 0 V to VDD - 0.4 V at RL = 10 kΩ and driving up to 100 pF load capacitance."+      },+      {+        "number": "8",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive single-supply input, 2.7 V to 5.5 V recommended with respect to AGND and 7 V absolute maximum."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: Pinout taken from the D (SOIC-8) package terminal table and the D-package top view on page 1. The TL; Pin descriptions for REF and OUTA/OUTB combine the terminal-table text with the electrical-character"+        ],+        "pages_sent": 27,+        "cost_usd": 0.0984,+        "at": "2026-10-08T14:40:38"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/tlv5638",+        "pages": 27,+        "sha256": "5e8282e329ce688a",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "tlv5638cdr.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          4.9,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "tlv5638cdr-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          4.9,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "b658b3118685eb04fdfe83a3e03d0b25fe3fc29935873bdb3cccce6280f860e3",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file