component
TLV5632IDWR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+56@@ -0,0 +1,56 @@+# TLV5632IDWR++**Texas Instruments** · Digital To Analog Converters (DACs) · SOIC-20-300mil++TLV5632IDWR from Texas Instruments, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DGND | power_in | Digital ground reference for the serial interface and digital logic. |+| 2 | DIN | input | Digital serial data input that receives the 16-bit word (4 control bits and 12 data bits) MSB first on falling SCLK edges. |+| 3 | SCLK | input | Serial clock input whose maximum frequency is 30 MHz, with a minimum high and low pulse of 16 ns each. |+| 4 | FS | input | Frame sync input whose falling edge starts a write cycle; in µC mode it must stay low until all 16 data bits are transferred. |+| 5 | PRE | input | Asynchronous preset input that, when driven low together with LDAC asserted, loads all DAC outputs from the preset register. |+| 6 | OUTE | output | DAC E analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ. |+| 7 | OUTF | output | DAC F analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ. |+| 8 | OUTG | output | DAC G analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ. |+| 9 | OUTH | output | DAC H analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ. |+| 10 | AGND | power_in | Analog ground reference for the DAC core, output buffers and reference. |+| 11 | AVDD | power_in | Analog power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation, and it must power up before DVDD for correct power-on reset. |+| 12 | OUTA | output | DAC A analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ. |+| 13 | OUTB | output | DAC B analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ. |+| 14 | OUTC | output | DAC C analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ. |+| 15 | OUTD | output | DAC D analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ. |+| 16 | REF | bidirectional | Reference input/output that accepts an external reference from 0 to AVDD or sources an internal 1.024 V or 2.048 V reference (up to 1 mA), which needs a 1 µF to 10 µF capacitor in parallel with 100 pF when internal reference is used. |+| 17 | MODE | input | DSP/µC mode select where high selects µC mode and not connected (or 0) selects DSP mode. |+| 18 | LDAC | input | Asynchronous load DAC input; DAC outputs update only while LDAC is low, with a minimum low pulse of 10 ns. |+| 19 | DOUT | output | Digital serial data output that repeats DIN data with a 16-clock delay for daisy-chaining when enabled through CTRL0. |+| 20 | DVDD | power_in | Digital power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation, and it must come up after AVDD. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-20-300mil |+| Category | ADC/DAC/Data Conversion |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `TLV5632IDWR`+- Footprint: `Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm`+- 3D model: SOIC-20-300mil (KiCad packages3D, STEP)+- 3D model files: `tlv5632idwr-etched.step` / `tlv5632idwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv5632idwr.step` / `tlv5632idwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlv5630) (25 pp, sha256 `fca921911e680eae`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlv5632idwr-datasheet.pdf)
page.jsonadded+270@@ -0,0 +1,270 @@+{+ "slug": "tlv5632idwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Digital To Analog Converters (DACs), SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "adc-dac-data conversion",+ "tlv5632idwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tlv5632idwr.kicad_sym",+ "tlv5632idwr.kicad_mod",+ "tlv5632idwr.glb",+ "tlv5632idwr.step",+ "tlv5632idwr.lbr",+ "docs/hero.png",+ "docs/tlv5632idwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tlv5632idwr-hero.glb",+ "tlv5632idwr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TLV5632IDWR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-20-300mil",+ "pin_count": 20,+ "category": "ADC/DAC/Data Conversion",+ "subcategory": "Digital To Analog Converters (DACs)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tlv5630",+ "parts": {+ "symbol": "tlv5632idwr.kicad_sym",+ "footprint": "tlv5632idwr.kicad_mod",+ "model_3d": "tlv5632idwr-hero.glb",+ "model_3d_plain": "tlv5632idwr.glb",+ "model_3d_step": "tlv5632idwr-etched.step",+ "model_3d_step_plain": "tlv5632idwr.step",+ "lbr": "tlv5632idwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2679760",+ "digikey": "TLV5632IDWR-ND",+ "mouser": "595-TLV5632IDWR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:16:15Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "TLV5632IDWR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TLV5632IDWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground reference for the serial interface and digital logic."+ },+ {+ "number": "2",+ "name": "DIN",+ "type": "input",+ "description": "Digital serial data input that receives the 16-bit word (4 control bits and 12 data bits) MSB first on falling SCLK edges."+ },+ {+ "number": "3",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input whose maximum frequency is 30 MHz, with a minimum high and low pulse of 16 ns each."+ },+ {+ "number": "4",+ "name": "FS",+ "type": "input",+ "description": "Frame sync input whose falling edge starts a write cycle; in µC mode it must stay low until all 16 data bits are transferred."+ },+ {+ "number": "5",+ "name": "PRE",+ "type": "input",+ "description": "Asynchronous preset input that, when driven low together with LDAC asserted, loads all DAC outputs from the preset register."+ },+ {+ "number": "6",+ "name": "OUTE",+ "type": "output",+ "description": "DAC E analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ."+ },+ {+ "number": "7",+ "name": "OUTF",+ "type": "output",+ "description": "DAC F analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ."+ },+ {+ "number": "8",+ "name": "OUTG",+ "type": "output",+ "description": "DAC G analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ."+ },+ {+ "number": "9",+ "name": "OUTH",+ "type": "output",+ "description": "DAC H analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ."+ },+ {+ "number": "10",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground reference for the DAC core, output buffers and reference."+ },+ {+ "number": "11",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation, and it must power up before DVDD for correct power-on reset."+ },+ {+ "number": "12",+ "name": "OUTA",+ "type": "output",+ "description": "DAC A analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ."+ },+ {+ "number": "13",+ "name": "OUTB",+ "type": "output",+ "description": "DAC B analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ."+ },+ {+ "number": "14",+ "name": "OUTC",+ "type": "output",+ "description": "DAC C analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ."+ },+ {+ "number": "15",+ "name": "OUTD",+ "type": "output",+ "description": "DAC D analog voltage output, rail-to-rail and short-circuit protected, with a specified range of 0 to AVDD − 0.4 V at RL = 10 kΩ."+ },+ {+ "number": "16",+ "name": "REF",+ "type": "bidirectional",+ "description": "Reference input/output that accepts an external reference from 0 to AVDD or sources an internal 1.024 V or 2.048 V reference (up to 1 mA), which needs a 1 µF to 10 µF capacitor in parallel with 100 pF when internal reference is used."+ },+ {+ "number": "17",+ "name": "MODE",+ "type": "input",+ "description": "DSP/µC mode select where high selects µC mode and not connected (or 0) selects DSP mode."+ },+ {+ "number": "18",+ "name": "LDAC",+ "type": "input",+ "description": "Asynchronous load DAC input; DAC outputs update only while LDAC is low, with a minimum low pulse of 10 ns."+ },+ {+ "number": "19",+ "name": "DOUT",+ "type": "output",+ "description": "Digital serial data output that repeats DIN data with a 16-clock delay for daisy-chaining when enabled through CTRL0."+ },+ {+ "number": "20",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital power supply, 4.5 V to 5.5 V for 5-V operation or 2.7 V to 3.3 V for 3-V operation, and it must come up after AVDD."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 25,+ "cost_usd": 0.1119,+ "at": "2026-10-08T16:15:51"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlv5630",+ "pages": 25,+ "sha256": "fca921911e680eae",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tlv5632idwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "59a10b341e6972b31d81802a048060326da627d8b92dcf4263064f4f62ec808e",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tlv5632idwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 10.3,+ 12.8,+ 2.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "eefaea364acfb8dde6eeb6b9d4897ff2bd3d83112ec90d2456082e63949c67f2",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}