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Initial commit: component/tlv5624cd

Ray ·a0cd49d221 ·18d ago
2 files changed +242
README.mdadded+44
@@ -0,0 +1,44 @@+# TLV5624CD++**Texas Instruments** · Digital To Analog Converters (DAC) · SOIC-8++TLV5624CD from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DIN | input | Digital serial data input; the 16-bit word (4 control bits and 8 data bits) is shifted in MSB first on high-to-low SCLK transitions. |+| 2 | SCLK | input | Digital serial clock input, with a maximum serial clock frequency of 20 MHz. |+| 3 | CS | input | Active-low chip select that enables or disables the serial inputs; it can be tied low in three-wire operation. |+| 4 | FS | input | Frame sync input; a falling edge starts the serial shift, and the DAC latch updates after 16 bits have been clocked in or when FS rises. |+| 5 | AGND | power_in | Analog ground reference for the DAC, to be connected to the system analog ground plane. |+| 6 | REF | bidirectional | Reference voltage input/output; requires a 0.1 µF bypass capacitor, plus a 10 µF capacitor when the internal reference is used, and the external reference must be selected in the control register when an external reference is applied (input range 0 V to VDD−1.5 V). |+| 7 | OUT | output | DAC A analog voltage output from the rail-to-rail x2 buffer, specified for a minimum load of 2 kΩ and a maximum load capacitance of 100 pF. |+| 8 | VDD | power_in | Positive power supply, 4.5 V to 5.5 V at VDD = 5 V nominal or 2.7 V to 3.3 V at VDD = 3 V nominal. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-8 |+| Category | Data Acquisition |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `TLV5624CD`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)+- 3D model files: `tlv5624cd-etched.step` / `tlv5624cd-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv5624cd.step` / `tlv5624cd.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlv5624) (26 pp, sha256 `5ae4849781b211d0`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlv5624cd-datasheet.pdf)
page.jsonadded+198
@@ -0,0 +1,198 @@+{+  "slug": "tlv5624cd",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Digital To Analog Converters (DAC), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "data acquisition",+    "tlv5624cd",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "tlv5624cd.kicad_sym",+    "tlv5624cd.kicad_mod",+    "tlv5624cd.glb",+    "tlv5624cd.step",+    "tlv5624cd.lbr",+    "docs/hero.png",+    "docs/tlv5624cd-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "tlv5624cd-hero.glb",+    "tlv5624cd-hero.overlay.json"+  ],+  "component": {+    "mpn": "TLV5624CD",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-8",+    "pin_count": 8,+    "category": "Data Acquisition",+    "subcategory": "Digital To Analog Converters (DAC)",+    "datasheet": "https://www.ti.com/cn/lit/gpn/tlv5624",+    "parts": {+      "symbol": "tlv5624cd.kicad_sym",+      "footprint": "tlv5624cd.kicad_mod",+      "model_3d": "tlv5624cd-hero.glb",+      "model_3d_plain": "tlv5624cd.glb",+      "model_3d_step": "tlv5624cd-etched.step",+      "model_3d_step_plain": "tlv5624cd.step",+      "lbr": "tlv5624cd.lbr"+    },+    "distributor_links": {+      "lcsc": "C1555102",+      "digikey": "2156-TLV5624CD-ND",+      "mouser": "595-TLV5624CD"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T14:40:33Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "2156-TLV5624CD-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "595-TLV5624CD",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "DIN",+        "type": "input",+        "description": "Digital serial data input; the 16-bit word (4 control bits and 8 data bits) is shifted in MSB first on high-to-low SCLK transitions."+      },+      {+        "number": "2",+        "name": "SCLK",+        "type": "input",+        "description": "Digital serial clock input, with a maximum serial clock frequency of 20 MHz."+      },+      {+        "number": "3",+        "name": "CS",+        "type": "input",+        "description": "Active-low chip select that enables or disables the serial inputs; it can be tied low in three-wire operation."+      },+      {+        "number": "4",+        "name": "FS",+        "type": "input",+        "description": "Frame sync input; a falling edge starts the serial shift, and the DAC latch updates after 16 bits have been clocked in or when FS rises."+      },+      {+        "number": "5",+        "name": "AGND",+        "type": "power_in",+        "description": "Analog ground reference for the DAC, to be connected to the system analog ground plane."+      },+      {+        "number": "6",+        "name": "REF",+        "type": "bidirectional",+        "description": "Reference voltage input/output; requires a 0.1 µF bypass capacitor, plus a 10 µF capacitor when the internal reference is used, and the external reference must be selected in the control register when an external reference is applied (input range 0 V to VDD−1.5 V)."+      },+      {+        "number": "7",+        "name": "OUT",+        "type": "output",+        "description": "DAC A analog voltage output from the rail-to-rail x2 buffer, specified for a minimum load of 2 kΩ and a maximum load capacitance of 100 pF."+      },+      {+        "number": "8",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive power supply, 4.5 V to 5.5 V at VDD = 5 V nominal or 2.7 V to 3.3 V at VDD = 3 V nominal."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 26,+        "cost_usd": 0.0931,+        "at": "2026-10-08T14:40:13"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/tlv5624",+        "pages": 26,+        "sha256": "5ae4849781b211d0",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 8,+        "described": 8,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "tlv5624cd.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          4.9,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "tlv5624cd-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          6,+          4.9,+          1.75+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "b9e6c27433c2535fe82f2c2d9a0f499cade8af95a972d0b8df96a3ecba56cc7b",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file