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TLV320AIC3104IRHBR
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Texas Instruments Audio Amplifiers, HVQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# TLV320AIC3104IRHBR++**Texas Instruments** · Audio Amplifiers · HVQFN-32-EP(5x5)++TLV320AIC3104IRHBR from Texas Instruments, in a HVQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | MCLK | input | Master clock input accepting frequencies from 512 kHz to 50 MHz for programmable clock generation to support standard audio sample rates. |+| 2 | BCLK | bidirectional | Audio serial data bus bit clock input/output configurable as slave input or master output with continuous or 256-clock transfer modes. |+| 3 | WCLK | bidirectional | Audio serial data bus word clock input/output configurable as slave input or master output to define frame boundaries at selected ADC/DAC sample rate. |+| 4 | DIN | input | Audio serial data bus data input supporting I2S, left-justified, right-justified, DSP, and TDM transfer modes with 16/20/24/32-bit data width. |+| 5 | DOUT | output | Audio serial data bus data output providing ADC/DAC data in selected transfer mode with programmable high-impedance control when no valid data. |+| 6 | DVSS | power_in | Digital core and I/O ground supply at 0 V providing reference for all digital and I/O circuits. |+| 7 | IOVDD | power_in | Digital I/O voltage supply operating range 1.1 V to 3.6 V for input/output buffer level translation. |+| 8 | SCL | bidirectional | I2C serial clock input/output with open-drain configuration supporting standard and fast mode I2C protocols for register access. |+| 9 | SDA | bidirectional | I2C serial data input/output with open-drain configuration for read/write access to device control and status registers. |+| 10 | MIC1LP/LINE1LP | input | Left channel input 1 configurable as single-ended input or positive terminal of fully differential input pair with 0 dB to -12 dB input level control. |+| 11 | MIC1LM/LINE1LM | input | Left channel differential input negative terminal for fully differential configuration of MIC1L/LINE1L pair. |+| 12 | MIC1RP/LINE1RP | input | Right channel input 1 configurable as single-ended input or positive terminal of fully differential input pair with 0 dB to -12 dB input level control. |+| 13 | MIC1RM/LINE1RM | input | Right channel differential input negative terminal for fully differential configuration of MIC1R/LINE1R pair. |+| 14 | MIC2L/LINE2L/MICDET | input | Left channel single-ended input 2 supporting microphone detection capability on the shared MICDET pin. |+| 15 | MICBIAS | power_out | Microphone bias voltage output programmed to 2 V, 2.5 V, AVDD, or powered down with 4-mA maximum current sourcing capability. |+| 16 | MIC2R/LINE2R | input | Right channel single-ended input 2 with programmable input level control from 0 dB to -12 dB in 1.5-dB steps. |+| 17 | AVSS1 | power_in | Analog ADC ground supply at 0 V providing reference for analog-to-digital converter front-end circuits. |+| 18 | DRVDD | power_in | Analog ADC and output driver voltage supply operating range 2.7 V to 3.6 V. |+| 19 | HPLOUT | output | High-power output driver left channel positive terminal capable of delivering 30 mW into 16-Ω single-ended load or used in bridge configuration. |+| 20 | HPLCOM | output | High-power output driver left channel negative/multi-functional terminal configurable as differential pair, constant VCM output, or independent single-ended driver. |+| 21 | DRVSS | power_in | Analog output driver ground supply at 0 V (connect device thermal pad to this pin for heat dissipation). |+| 22 | HPRCOM | output | High-power output driver right channel negative/multi-functional terminal configurable as differential pair, constant VCM output, or independent single-ended driver. |+| 23 | HPROUT | output | High-power output driver right channel positive terminal capable of delivering 30 mW into 16-Ω single-ended load or used in bridge configuration. |+| 24 | DRVDD | power_in | Analog output driver voltage supply operating range 2.7 V to 3.6 V. |+| 25 | AVDD | power_in | Analog DAC voltage supply operating range 2.7 V to 3.6 V for DAC and analog input front-end circuits. |+| 26 | AVSS2 | power_in | Analog DAC ground supply at 0 V providing reference for digital-to-analog converter circuits. |+| 27 | LEFT_LOP | output | Left line output positive terminal driving fully differential stereo line output with 10-kΩ load and 0 dB to -78 dB output volume control. |+| 28 | LEFT_LOM | output | Left line output negative terminal driving fully differential stereo line output with 10-kΩ load and 0 dB to -78 dB output volume control. |+| 29 | RIGHT_LOP | output | Right line output positive terminal driving fully differential stereo line output with 10-kΩ load and 0 dB to -78 dB output volume control. |+| 30 | RIGHT_LOM | output | Right line output negative terminal driving fully differential stereo line output with 10-kΩ load and 0 dB to -78 dB output volume control. |+| 31 | RESET | input | Reset input (active low) requiring minimum 10 ns pulse to initialize all registers to default state after power-up. |+| 32 | DVDD | power_in | Digital core voltage supply operating range 1.525 V to 1.95 V for all digital signal processing and logic circuits. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HVQFN-32-EP(5x5) |+| Category | Amplifiers/Comparators |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `TLV320AIC3104IRHBR`+- Footprint: `Package_DFN_QFN:HVQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm`+- 3D model: HVQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `tlv320aic3104irhbr-etched.step` / `tlv320aic3104irhbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlv320aic3104irhbr.step` / `tlv320aic3104irhbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlv320aic3104) (104 pp, sha256 `8cc627b2d4e0371b`, retrieved 2026-10-01, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlv320aic3104irhbr-datasheet.pdf)
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"model_3d_plain": "tlv320aic3104irhbr.glb",+ "model_3d_step": "tlv320aic3104irhbr-etched.step",+ "model_3d_step_plain": "tlv320aic3104irhbr.step",+ "lbr": "tlv320aic3104irhbr.lbr"+ },+ "distributor_links": {+ "lcsc": "C181753",+ "digikey": "296-26818-2-ND",+ "mouser": "595-TLV320C3104IRHBR"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T17:21:16Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-26818-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-TLV320C3104IRHBR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "MCLK",+ "type": "input",+ "description": "Master clock input accepting frequencies from 512 kHz to 50 MHz for programmable clock generation to support standard audio sample rates."+ },+ {+ "number": "2",+ "name": "BCLK",+ "type": "bidirectional",+ "description": "Audio serial data bus bit clock input/output configurable as slave input or master output with continuous or 256-clock transfer modes."+ },+ {+ "number": "3",+ "name": "WCLK",+ "type": "bidirectional",+ "description": "Audio serial data bus word clock input/output configurable as slave input or master output to define frame boundaries at selected ADC/DAC sample rate."+ },+ {+ "number": "4",+ "name": "DIN",+ "type": "input",+ "description": "Audio serial data bus data input supporting I2S, left-justified, right-justified, DSP, and TDM transfer modes with 16/20/24/32-bit data width."+ },+ {+ "number": "5",+ "name": "DOUT",+ "type": "output",+ "description": "Audio serial data bus data output providing ADC/DAC data in selected transfer mode with programmable high-impedance control when no valid data."+ },+ {+ "number": "6",+ "name": "DVSS",+ "type": "power_in",+ "description": "Digital core and I/O ground supply at 0 V providing reference for all digital and I/O circuits."+ },+ {+ "number": "7",+ "name": "IOVDD",+ "type": "power_in",+ "description": "Digital I/O voltage supply operating range 1.1 V to 3.6 V for input/output buffer level translation."+ },+ {+ "number": "8",+ "name": "SCL",+ "type": "bidirectional",+ "description": "I2C serial clock input/output with open-drain configuration supporting standard and fast mode I2C protocols for register access."+ },+ {+ "number": "9",+ "name": "SDA",+ "type": "bidirectional",+ "description": "I2C serial data input/output with open-drain configuration for read/write access to device control and status registers."+ },+ {+ "number": "10",+ "name": "MIC1LP/LINE1LP",+ "type": "input",+ "description": "Left channel input 1 configurable as single-ended input or positive terminal of fully differential input pair with 0 dB to -12 dB input level control."+ },+ {+ "number": "11",+ "name": "MIC1LM/LINE1LM",+ "type": "input",+ "description": "Left channel differential input negative terminal for fully differential configuration of MIC1L/LINE1L pair."+ },+ {+ "number": "12",+ "name": "MIC1RP/LINE1RP",+ "type": "input",+ "description": "Right channel input 1 configurable as single-ended input or positive terminal of fully differential input pair with 0 dB to -12 dB input level control."+ },+ {+ "number": "13",+ "name": "MIC1RM/LINE1RM",+ "type": "input",+ "description": "Right channel differential input negative terminal for fully differential configuration of MIC1R/LINE1R pair."+ },+ {+ "number": "14",+ "name": "MIC2L/LINE2L/MICDET",+ "type": "input",+ "description": "Left channel single-ended input 2 supporting microphone detection capability on the shared MICDET pin."+ },+ {+ "number": "15",+ "name": "MICBIAS",+ "type": "power_out",+ "description": "Microphone bias voltage output programmed to 2 V, 2.5 V, AVDD, or powered down with 4-mA maximum current sourcing capability."+ },+ {+ "number": "16",+ "name": "MIC2R/LINE2R",+ "type": "input",+ "description": "Right channel single-ended input 2 with programmable input level control from 0 dB to -12 dB in 1.5-dB steps."+ },+ {+ "number": "17",+ "name": "AVSS1",+ "type": "power_in",+ "description": "Analog ADC ground supply at 0 V providing reference for analog-to-digital converter front-end circuits."+ },+ {+ "number": "18",+ "name": "DRVDD",+ "type": "power_in",+ "description": "Analog ADC and output driver voltage supply operating range 2.7 V to 3.6 V."+ },+ {+ "number": "19",+ "name": "HPLOUT",+ "type": "output",+ "description": "High-power output driver left channel positive terminal capable of delivering 30 mW into 16-Ω single-ended load or used in bridge configuration."+ },+ {+ "number": "20",+ "name": "HPLCOM",+ "type": "output",+ "description": "High-power output driver left channel negative/multi-functional terminal configurable as differential pair, constant VCM output, or independent single-ended driver."+ },+ {+ "number": "21",+ "name": "DRVSS",+ "type": "power_in",+ "description": "Analog output driver ground supply at 0 V (connect device thermal pad to this pin for heat dissipation)."+ },+ {+ "number": "22",+ "name": "HPRCOM",+ "type": "output",+ "description": "High-power output driver right channel negative/multi-functional terminal configurable as differential pair, constant VCM output, or independent single-ended driver."+ },+ {+ "number": "23",+ "name": "HPROUT",+ "type": "output",+ "description": "High-power output driver right channel positive terminal capable of delivering 30 mW into 16-Ω single-ended load or used in bridge configuration."+ },+ {+ "number": "24",+ "name": "DRVDD",+ "type": "power_in",+ "description": "Analog output driver voltage supply operating range 2.7 V to 3.6 V."+ },+ {+ "number": "25",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog DAC voltage supply operating range 2.7 V to 3.6 V for DAC and analog input front-end circuits."+ },+ {+ "number": "26",+ "name": "AVSS2",+ "type": "power_in",+ "description": "Analog DAC ground supply at 0 V providing reference for digital-to-analog converter circuits."+ },+ {+ "number": "27",+ "name": "LEFT_LOP",+ "type": "output",+ "description": "Left line output positive terminal driving fully differential stereo line output with 10-kΩ load and 0 dB to -78 dB output volume control."+ },+ {+ "number": "28",+ "name": "LEFT_LOM",+ "type": "output",+ "description": "Left line output negative terminal driving fully differential stereo line output with 10-kΩ load and 0 dB to -78 dB output volume control."+ },+ {+ "number": "29",+ "name": "RIGHT_LOP",+ "type": "output",+ "description": "Right line output positive terminal driving fully differential stereo line output with 10-kΩ load and 0 dB to -78 dB output volume control."+ },+ {+ "number": "30",+ "name": "RIGHT_LOM",+ "type": "output",+ "description": "Right line output negative terminal driving fully differential stereo line output with 10-kΩ load and 0 dB to -78 dB output volume control."+ },+ {+ "number": "31",+ "name": "RESET",+ "type": "input",+ "description": "Reset input (active low) requiring minimum 10 ns pulse to initialize all registers to default state after power-up."+ },+ {+ "number": "32",+ "name": "DVDD",+ "type": "power_in",+ "description": "Digital core voltage supply operating range 1.525 V to 1.95 V for all digital signal processing and logic circuits."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 104,+ "cost_usd": 0.8982,+ "at": "2026-10-01T17:20:57"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlv320aic3104",+ "pages": 104,+ "sha256": "8cc627b2d4e0371b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}