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TLK1501IRCPR
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Texas Instruments Ethernet Transceivers, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+100@@ -0,0 +1,100 @@+# TLK1501IRCPR++**Texas Instruments** · Ethernet Transceivers · LQFP-64(10x10)++TLK1501IRCPR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDD | power_in | Digital logic power supply for all digital circuitry and digital I/O buffers; the device uses a 2.5-V supply with 3-V compatible I/O. |+| 2 | TXD3 | input | Transmit data bus bit 3, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 3 | TXD4 | input | Transmit data bus bit 4, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 4 | TXD5 | input | Transmit data bus bit 5, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 5 | GND | power_in | Digital logic ground providing the return for logic circuits and digital I/O buffers. |+| 6 | TXD6 | input | Transmit data bus bit 6, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 7 | TXD7 | input | Transmit data bus bit 7, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 8 | GTX_CLK | input | Continuous reference clock input in the 30 MHz to 75 MHz range whose rising edge registers TXD, TX_EN and TX_ER for serialization. |+| 9 | VDD | power_in | Digital logic power supply for all digital circuitry and digital I/O buffers. |+| 10 | TXD8 | input | Transmit data bus bit 8, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 11 | TXD9 | input | Transmit data bus bit 9, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 12 | TXD10 | input | Transmit data bus bit 10, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 13 | GND | power_in | Digital logic ground providing the return for logic circuits and digital I/O buffers. |+| 14 | TXD11 | input | Transmit data bus bit 11, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 15 | TXD12 | input | Transmit data bus bit 12, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 16 | TXD13 | input | Transmit data bus bit 13, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 17 | TXD14 | input | Transmit data bus bit 14, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 18 | GND | power_in | Digital logic ground providing the return for logic circuits and digital I/O buffers. |+| 19 | TXD15 | input | Transmit data bus bit 15, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 20 | TX_EN | input | Transmit enable with internal pulldown that must be high with the first preamble word and negated before the first GTX_CLK rising edge after the final word of a frame. |+| 21 | LOOPEN | input | Loop enable with internal pulldown; when high it routes transmit data internally to the receiver and holds DOUTTXP/DOUTTXN high-impedance, and it must be held low in normal operation. |+| 22 | TX_ER | input | Transmit error coding with internal pulldown; when high together with TX_EN it flags an error in the frame being transferred. |+| 23 | VDD | power_in | Digital logic power supply for all digital circuitry and digital I/O buffers. |+| 24 | ENABLE | input | Device enable with pullup; holding it low places the device in power-down mode with only the serial receive signal detect active, and asserting it high while powered down triggers power-on reset. |+| 25 | LCKREFN | input | Lock-to-reference input with pullup; when low the receiver clock is frequency locked to GTX_CLK, the device is transmit-only, and RXD[0:15], RX_CLK, RX_ER and RX_DV/LOS go high-impedance. |+| 26 | PRBSEN | input | PRBS test enable with internal pulldown; when high, PRBS test results are monitored on RX_ER/PRBS_PASS, where high indicates valid PRBS is being received. |+| 27 | TESTEN | input | Test mode enable with internal pulldown that should be left unconnected or tied low. |+| 28 | GND | power_in | Digital logic ground providing the return for logic circuits and digital I/O buffers. |+| 29 | RX_ER/PRBS_PASS | output | Receive error output when PRBSEN is low (asserted during data errors and carrier extension), or PRBS pass status when PRBSEN is high (high = pass); high-impedance during power-on reset. |+| 30 | RX_DV/LOS | output | Receive data valid output asserted across each recovered frame, and asserted high with RX_ER and the receive data bus as a loss-of-signal indication when the serial receive differential amplitude falls below 200 mV; high-impedance during power-on reset. |+| 31 | RXD15 | output | Receive data bus bit 15, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 32 | RXD14 | output | Receive data bus bit 14, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 33 | GND | power_in | Digital logic ground providing the return for logic circuits and digital I/O buffers. |+| 34 | RXD13 | output | Receive data bus bit 13, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 35 | RXD12 | output | Receive data bus bit 12, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 36 | RXD11 | output | Receive data bus bit 11, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 37 | RXD10 | output | Receive data bus bit 10, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 38 | VDD | power_in | Digital logic power supply for all digital circuitry and digital I/O buffers. |+| 39 | RXD9 | output | Receive data bus bit 9, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 40 | RXD8 | output | Receive data bus bit 8, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 41 | RX_CLK | output | Recovered clock output at the serial data rate divided by 20, synchronized to RXD, RX_ER and RX_DV/LOS, held low during power-on reset. |+| 42 | RXD7 | output | Receive data bus bit 7, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 43 | GND | power_in | Digital logic ground providing the return for logic circuits and digital I/O buffers. |+| 44 | RXD6 | output | Receive data bus bit 6, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 45 | RXD5 | output | Receive data bus bit 5, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 46 | RXD4 | output | Receive data bus bit 4, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 47 | RXD3 | output | Receive data bus bit 3, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 48 | VDD | power_in | Digital logic power supply for all digital circuitry and digital I/O buffers. |+| 49 | RXD2 | output | Receive data bus bit 2, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 50 | RXD1 | output | Receive data bus bit 1, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 51 | RXD0 | output | Receive data bus bit 0, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset. |+| 52 | GNDA | power_in | Analog ground providing the reference for the high-speed RX and TX analog circuits. |+| 53 | DINRXN | input | Negative side of the differential serial receive input from a copper or optical interface module, used together with DINRXP. |+| 54 | DINRXP | input | Positive side of the differential serial receive input from a copper or optical interface module, used together with DINRXN. |+| 55 | VDDA | power_in | Analog power supply reference for the high-speed receiver and transmitter circuits. |+| 56 | RREF | input | Connection for an external reference resistor returned to analog VDD, which sets an accurate current reference for the transmitter circuitry. |+| 57 | VDDA | power_in | Analog power supply reference for the high-speed receiver and transmitter circuits. |+| 58 | GNDA | power_in | Analog ground providing the reference for the high-speed RX and TX analog circuits. |+| 59 | DOUTTXN | output | Negative side of the differential serial transmit output carrying NRZ data at 20 times GTX_CLK; high-impedance on power-up and while LOOPEN is high. |+| 60 | DOUTTXP | output | Positive side of the differential serial transmit output carrying NRZ data at 20 times GTX_CLK; high-impedance on power-up and while LOOPEN is high. |+| 61 | GNDA | power_in | Analog ground providing the reference for the high-speed RX and TX analog circuits. |+| 62 | TXD0 | input | Transmit data bus bit 0 (LSB, transmitted first), one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 63 | TXD1 | input | Transmit data bus bit 1, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |+| 64 | TXD2 | input | Transmit data bus bit 2, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | LQFP-64(10x10) |+| Category | Interface |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `TLK1501IRCPR`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `tlk1501ircpr-etched.step` / `tlk1501ircpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlk1501ircpr.step` / `tlk1501ircpr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlk1501) (34 pp, sha256 `9ca14157aaacc1b3`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlk1501ircpr-datasheet.pdf)
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the device uses a 2.5-V supply with 3-V compatible I/O."+ },+ {+ "number": "2",+ "name": "TXD3",+ "type": "input",+ "description": "Transmit data bus bit 3, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "3",+ "name": "TXD4",+ "type": "input",+ "description": "Transmit data bus bit 4, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "4",+ "name": "TXD5",+ "type": "input",+ "description": "Transmit data bus bit 5, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Digital logic ground providing the return for logic circuits and digital I/O buffers."+ },+ {+ "number": "6",+ "name": "TXD6",+ "type": "input",+ "description": "Transmit data bus bit 6, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "7",+ "name": "TXD7",+ "type": "input",+ "description": "Transmit data bus bit 7, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "8",+ "name": "GTX_CLK",+ "type": "input",+ "description": "Continuous reference clock input in the 30 MHz to 75 MHz range whose rising edge registers TXD, TX_EN and TX_ER for serialization."+ },+ {+ "number": "9",+ "name": "VDD",+ "type": "power_in",+ "description": "Digital logic power supply for all digital circuitry and digital I/O buffers."+ },+ {+ "number": "10",+ "name": "TXD8",+ "type": "input",+ "description": "Transmit data bus bit 8, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "11",+ "name": "TXD9",+ "type": "input",+ "description": "Transmit data bus bit 9, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "12",+ "name": "TXD10",+ "type": "input",+ "description": "Transmit data bus bit 10, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "13",+ "name": "GND",+ "type": "power_in",+ "description": "Digital logic ground providing the return for logic circuits and digital I/O buffers."+ },+ {+ "number": "14",+ "name": "TXD11",+ "type": "input",+ "description": "Transmit data bus bit 11, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "15",+ "name": "TXD12",+ "type": "input",+ "description": "Transmit data bus bit 12, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "16",+ "name": "TXD13",+ "type": "input",+ "description": "Transmit data bus bit 13, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "17",+ "name": "TXD14",+ "type": "input",+ "description": "Transmit data bus bit 14, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "18",+ "name": "GND",+ "type": "power_in",+ "description": "Digital logic ground providing the return for logic circuits and digital I/O buffers."+ },+ {+ "number": "19",+ "name": "TXD15",+ "type": "input",+ "description": "Transmit data bus bit 15, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "20",+ "name": "TX_EN",+ "type": "input",+ "description": "Transmit enable with internal pulldown that must be high with the first preamble word and negated before the first GTX_CLK rising edge after the final word of a frame."+ },+ {+ "number": "21",+ "name": "LOOPEN",+ "type": "input",+ "description": "Loop enable with internal pulldown; when high it routes transmit data internally to the receiver and holds DOUTTXP/DOUTTXN high-impedance, and it must be held low in normal operation."+ },+ {+ "number": "22",+ "name": "TX_ER",+ "type": "input",+ "description": "Transmit error coding with internal pulldown; when high together with TX_EN it flags an error in the frame being transferred."+ },+ {+ "number": "23",+ "name": "VDD",+ "type": "power_in",+ "description": "Digital logic power supply for all digital circuitry and digital I/O buffers."+ },+ {+ "number": "24",+ "name": "ENABLE",+ "type": "input",+ "description": "Device enable with pullup; holding it low places the device in power-down mode with only the serial receive signal detect active, and asserting it high while powered down triggers power-on reset."+ },+ {+ "number": "25",+ "name": "LCKREFN",+ "type": "input",+ "description": "Lock-to-reference input with pullup; when low the receiver clock is frequency locked to GTX_CLK, the device is transmit-only, and RXD[0:15], RX_CLK, RX_ER and RX_DV/LOS go high-impedance."+ },+ {+ "number": "26",+ "name": "PRBSEN",+ "type": "input",+ "description": "PRBS test enable with internal pulldown; when high, PRBS test results are monitored on RX_ER/PRBS_PASS, where high indicates valid PRBS is being received."+ },+ {+ "number": "27",+ "name": "TESTEN",+ "type": "input",+ "description": "Test mode enable with internal pulldown that should be left unconnected or tied low."+ },+ {+ "number": "28",+ "name": "GND",+ "type": "power_in",+ "description": "Digital logic ground providing the return for logic circuits and digital I/O buffers."+ },+ {+ "number": "29",+ "name": "RX_ER/PRBS_PASS",+ "type": "output",+ "description": "Receive error output when PRBSEN is low (asserted during data errors and carrier extension), or PRBS pass status when PRBSEN is high (high = pass); high-impedance during power-on reset."+ },+ {+ "number": "30",+ "name": "RX_DV/LOS",+ "type": "output",+ "description": "Receive data valid output asserted across each recovered frame, and asserted high with RX_ER and the receive data bus as a loss-of-signal indication when the serial receive differential amplitude falls below 200 mV; high-impedance during power-on reset."+ },+ {+ "number": "31",+ "name": "RXD15",+ "type": "output",+ "description": "Receive data bus bit 15, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "32",+ "name": "RXD14",+ "type": "output",+ "description": "Receive data bus bit 14, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "33",+ "name": "GND",+ "type": "power_in",+ "description": "Digital logic ground providing the return for logic circuits and digital I/O buffers."+ },+ {+ "number": "34",+ "name": "RXD13",+ "type": "output",+ "description": "Receive data bus bit 13, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "35",+ "name": "RXD12",+ "type": "output",+ "description": "Receive data bus bit 12, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "36",+ "name": "RXD11",+ "type": "output",+ "description": "Receive data bus bit 11, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "37",+ "name": "RXD10",+ "type": "output",+ "description": "Receive data bus bit 10, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "38",+ "name": "VDD",+ "type": "power_in",+ "description": "Digital logic power supply for all digital circuitry and digital I/O buffers."+ },+ {+ "number": "39",+ "name": "RXD9",+ "type": "output",+ "description": "Receive data bus bit 9, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "40",+ "name": "RXD8",+ "type": "output",+ "description": "Receive data bus bit 8, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "41",+ "name": "RX_CLK",+ "type": "output",+ "description": "Recovered clock output at the serial data rate divided by 20, synchronized to RXD, RX_ER and RX_DV/LOS, held low during power-on reset."+ },+ {+ "number": "42",+ "name": "RXD7",+ "type": "output",+ "description": "Receive data bus bit 7, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "43",+ "name": "GND",+ "type": "power_in",+ "description": "Digital logic ground providing the return for logic circuits and digital I/O buffers."+ },+ {+ "number": "44",+ "name": "RXD6",+ "type": "output",+ "description": "Receive data bus bit 6, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "45",+ "name": "RXD5",+ "type": "output",+ "description": "Receive data bus bit 5, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "46",+ "name": "RXD4",+ "type": "output",+ "description": "Receive data bus bit 4, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "47",+ "name": "RXD3",+ "type": "output",+ "description": "Receive data bus bit 3, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "48",+ "name": "VDD",+ "type": "power_in",+ "description": "Digital logic power supply for all digital circuitry and digital I/O buffers."+ },+ {+ "number": "49",+ "name": "RXD2",+ "type": "output",+ "description": "Receive data bus bit 2, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "50",+ "name": "RXD1",+ "type": "output",+ "description": "Receive data bus bit 1, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "51",+ "name": "RXD0",+ "type": "output",+ "description": "Receive data bus bit 0, 16-bit parallel output synchronized to RX_CLK and valid on its rising edge; high-impedance during power-on reset."+ },+ {+ "number": "52",+ "name": "GNDA",+ "type": "power_in",+ "description": "Analog ground providing the reference for the high-speed RX and TX analog circuits."+ },+ {+ "number": "53",+ "name": "DINRXN",+ "type": "input",+ "description": "Negative side of the differential serial receive input from a copper or optical interface module, used together with DINRXP."+ },+ {+ "number": "54",+ "name": "DINRXP",+ "type": "input",+ "description": "Positive side of the differential serial receive input from a copper or optical interface module, used together with DINRXN."+ },+ {+ "number": "55",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power supply reference for the high-speed receiver and transmitter circuits."+ },+ {+ "number": "56",+ "name": "RREF",+ "type": "input",+ "description": "Connection for an external reference resistor returned to analog VDD, which sets an accurate current reference for the transmitter circuitry."+ },+ {+ "number": "57",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power supply reference for the high-speed receiver and transmitter circuits."+ },+ {+ "number": "58",+ "name": "GNDA",+ "type": "power_in",+ "description": "Analog ground providing the reference for the high-speed RX and TX analog circuits."+ },+ {+ "number": "59",+ "name": "DOUTTXN",+ "type": "output",+ "description": "Negative side of the differential serial transmit output carrying NRZ data at 20 times GTX_CLK; high-impedance on power-up and while LOOPEN is high."+ },+ {+ "number": "60",+ "name": "DOUTTXP",+ "type": "output",+ "description": "Positive side of the differential serial transmit output carrying NRZ data at 20 times GTX_CLK; high-impedance on power-up and while LOOPEN is high."+ },+ {+ "number": "61",+ "name": "GNDA",+ "type": "power_in",+ "description": "Analog ground providing the reference for the high-speed RX and TX analog circuits."+ },+ {+ "number": "62",+ "name": "TXD0",+ "type": "input",+ "description": "Transmit data bus bit 0 (LSB, transmitted first), one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "63",+ "name": "TXD1",+ "type": "input",+ "description": "Transmit data bus bit 1, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ },+ {+ "number": "64",+ "name": "TXD2",+ "type": "input",+ "description": "Transmit data bus bit 2, one of 16 single-ended TTL parallel data inputs clocked in on the rising edge of GTX_CLK."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package mismatch: the hint says LQFP-64 (10x10), but the datasheet describes a 64-pin VQFP/PowerPAD ; The pin-to-number map was taken from the garbled top-view figure on page 3 and checked against the T; The exposed PowerPAD on the package bottom has no pin number in the supplied text and is not listed."+ ],+ "pages_sent": 10,+ "cost_usd": 0.1038,+ "at": "2026-10-08T01:55:33"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlk1501",+ "pages": 34,+ "sha256": "9ca14157aaacc1b3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tlk1501ircpr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b0c827bc5c05552175d28affe44a5bd2ab45c9c36efff6ff07a74cc449b13db4",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tlk1501ircpr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "c5e71b2f9117a9376cce83af7a36c9de04bb5a29fa4138c7203c655094f74d7c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}