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TLC5615CDGKR
Public Made by Adomby adom
Texas Instruments Digital To Analog Converters (DACs), VSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+44@@ -0,0 +1,44 @@+# TLC5615CDGKR++**Texas Instruments** · Digital To Analog Converters (DACs) · VSSOP-8++TLC5615CDGKR from Texas Instruments, in a VSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DIN | input | Serial data input, read into the 16-bit shift register MSB first while CS is low; logic levels are VIH of at least 2.4 V and VIL of at most 0.8 V at VDD = 5 V. |+| 2 | SCLK | input | Serial clock input whose rising edge shifts data into the input register; it should be held low when CS is high to minimize clock feedthrough, and the maximum rate is about 14 MHz. |+| 3 | CS | input | Active-low chip select; the rising edge of CS transfers the shift register contents to the DAC register, and CS transitions should occur only while SCLK is low. |+| 4 | DOUT | output | Serial data output for daisy-chaining, delayed 16 clock cycles plus one clock width from DIN; it is a totem-pole output that changes on the SCLK falling edge when CS is low and stays at its last bit when CS is high. |+| 5 | AGND | power_in | Analog ground reference for the DAC and output buffer, which should connect to the system analog ground plane with negligible ground drop. |+| 6 | REFIN | input | Buffered high-impedance reference input (about 10 MΩ) whose voltage range is 0 V to VDD-2 V with a nominal 2.048 V, setting the full-scale output to twice the reference voltage. |+| 7 | OUT | output | DAC analog voltage output, rail-to-rail with short-circuit protection, with a range of 0 V to VDD-0.4 V at RL = 10 kΩ and capable of driving a 2 kΩ load. |+| 8 | VDD | power_in | Positive supply, 4.5 V to 5.5 V (5 V nominal), that should be bypassed to AGND with a 0.1 µF ceramic capacitor placed close to the device; absolute maximum is 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VSSOP-8 |+| Category | ADC/DAC/Data Conversion |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `TLC5615CDGKR`+- Footprint: `Package_SO:VSSOP-8_2.3x2mm_P0.5mm`+- 3D model: VSSOP-8 (KiCad packages3D, STEP)+- 3D model files: `tlc5615cdgkr-etched.step` / `tlc5615cdgkr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc5615cdgkr.step` / `tlc5615cdgkr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlc5615) (26 pp, sha256 `48b84c422b1f250c`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlc5615cdgkr-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "adc-dac-data conversion",+ "tlc5615cdgkr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tlc5615cdgkr.kicad_sym",+ "tlc5615cdgkr.kicad_mod",+ "tlc5615cdgkr.glb",+ "tlc5615cdgkr.step",+ "tlc5615cdgkr.lbr",+ "docs/hero.png",+ "docs/tlc5615cdgkr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tlc5615cdgkr-hero.glb",+ "tlc5615cdgkr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TLC5615CDGKR",+ "manufacturer": "Texas Instruments",+ "package": "VSSOP-8",+ "pin_count": 8,+ "category": "ADC/DAC/Data Conversion",+ "subcategory": "Digital To Analog Converters (DACs)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tlc5615",+ "parts": {+ "symbol": "tlc5615cdgkr.kicad_sym",+ "footprint": "tlc5615cdgkr.kicad_mod",+ "model_3d": "tlc5615cdgkr-hero.glb",+ "model_3d_plain": "tlc5615cdgkr.glb",+ "model_3d_step": "tlc5615cdgkr-etched.step",+ "model_3d_step_plain": "tlc5615cdgkr.step",+ "lbr": "tlc5615cdgkr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2679649",+ "digikey": "TLC5615CDGKR-ND",+ "mouser": "595-TLC5615CDGKR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T02:38:15Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "TLC5615CDGKR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TLC5615CDGKR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "DIN",+ "type": "input",+ "description": "Serial data input, read into the 16-bit shift register MSB first while CS is low; logic levels are VIH of at least 2.4 V and VIL of at most 0.8 V at VDD = 5 V."+ },+ {+ "number": "2",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input whose rising edge shifts data into the input register; it should be held low when CS is high to minimize clock feedthrough, and the maximum rate is about 14 MHz."+ },+ {+ "number": "3",+ "name": "CS",+ "type": "input",+ "description": "Active-low chip select; the rising edge of CS transfers the shift register contents to the DAC register, and CS transitions should occur only while SCLK is low."+ },+ {+ "number": "4",+ "name": "DOUT",+ "type": "output",+ "description": "Serial data output for daisy-chaining, delayed 16 clock cycles plus one clock width from DIN; it is a totem-pole output that changes on the SCLK falling edge when CS is low and stays at its last bit when CS is high."+ },+ {+ "number": "5",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground reference for the DAC and output buffer, which should connect to the system analog ground plane with negligible ground drop."+ },+ {+ "number": "6",+ "name": "REFIN",+ "type": "input",+ "description": "Buffered high-impedance reference input (about 10 MΩ) whose voltage range is 0 V to VDD-2 V with a nominal 2.048 V, setting the full-scale output to twice the reference voltage."+ },+ {+ "number": "7",+ "name": "OUT",+ "type": "output",+ "description": "DAC analog voltage output, rail-to-rail with short-circuit protection, with a range of 0 V to VDD-0.4 V at RL = 10 kΩ and capable of driving a 2 kΩ load."+ },+ {+ "number": "8",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply, 4.5 V to 5.5 V (5 V nominal), that should be bypassed to AGND with a 0.1 µF ceramic capacitor placed close to the device; absolute maximum is 7 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 26,+ "cost_usd": 0.0931,+ "at": "2026-10-08T02:38:00"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlc5615",+ "pages": 26,+ "sha256": "48b84c422b1f250c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tlc5615cdgkr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.1,+ 2,+ 0.85+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "353552981eef35cb93635057d4aeb89aef22648c77af6fd095e328bfe6b834bd",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tlc5615cdgkr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 3.1,+ 2,+ 0.85+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "fc6d6eb4d485543ca987a49a240c38718144ca9fb3a39a98185121bee67e4f9f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}