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TLC0834CDR
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Texas Instruments Analog To Digital Converters (ADC), SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# TLC0834CDR++**Texas Instruments** · Analog To Digital Converters (ADC) · SOIC-14++TLC0834CDR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NC | unconnected | No internal connection. |+| 2 | CS | input | Chip select; set low to enable all logic circuits and hold low for the complete conversion, and a high level clears the internal registers and puts the outputs in high impedance. |+| 3 | CH0 | input | Analog multiplexer input channel 0, usable single-ended or as a differential pair with CH1, with input range -0.3 V to VCC + 0.3 V. |+| 4 | CH1 | input | Analog multiplexer input channel 1, usable single-ended or as a differential pair with CH0, with input range -0.3 V to VCC + 0.3 V. |+| 5 | CH2 | input | Analog multiplexer input channel 2, usable single-ended or as a differential pair with CH3, with input range -0.3 V to VCC + 0.3 V. |+| 6 | CH3 | input | Analog multiplexer input channel 3, usable single-ended or as a differential pair with CH2, with input range -0.3 V to VCC + 0.3 V. |+| 7 | DGTL GND | power_in | Digital ground terminal, the reference for the network ground voltages. |+| 8 | ANLG GND | power_in | Analog ground terminal. |+| 9 | REF | input | Voltage reference input with 1.3 to 5.9 kΩ input resistance, adjustable to encode a smaller analog span to the full 8 bits (5 V reference typical). |+| 10 | DO | tri_state | Serial data output that shifts out the conversion result MSB first then LSB first, high-impedance when CS is high. |+| 11 | SARS | tri_state | SAR status output that goes high while a conversion is in progress and low after eight clock periods, high-impedance when CS is high. |+| 12 | CLK | input | Clock input from the processor with recommended frequency 10 kHz to 600 kHz and 40% to 60% duty cycle; DI is latched on each low-to-high transition. |+| 13 | DI | input | Serial data input that shifts the start bit and multiplexer address word into the converter on CLK rising edges, with TTL/MOS-compatible levels (VIH 2 V min, VIL 0.8 V max). |+| 14 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V recommended (5 V nominal), 6.5 V absolute maximum. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14 |+| Category | Data Acquisition |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `TLC0834CDR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)+- 3D model files: `tlc0834cdr-etched.step` / `tlc0834cdr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc0834cdr.step` / `tlc0834cdr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlc0838) (19 pp, sha256 `7da8a03a60087fd9`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlc0834cdr-datasheet.pdf)
page.jsonadded+236@@ -0,0 +1,236 @@+{+ "slug": "tlc0834cdr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Analog To Digital Converters (ADC), SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "data acquisition",+ "tlc0834cdr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tlc0834cdr.kicad_sym",+ "tlc0834cdr.kicad_mod",+ "tlc0834cdr.glb",+ "tlc0834cdr.step",+ "tlc0834cdr.lbr",+ "docs/hero.png",+ "docs/tlc0834cdr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tlc0834cdr-hero.glb",+ "tlc0834cdr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TLC0834CDR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14",+ "pin_count": 14,+ "category": "Data Acquisition",+ "subcategory": "Analog To Digital Converters (ADC)",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tlc0838",+ "parts": {+ "symbol": "tlc0834cdr.kicad_sym",+ "footprint": "tlc0834cdr.kicad_mod",+ "model_3d": "tlc0834cdr-hero.glb",+ "model_3d_plain": "tlc0834cdr.glb",+ "model_3d_step": "tlc0834cdr-etched.step",+ "model_3d_step_plain": "tlc0834cdr.step",+ "lbr": "tlc0834cdr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2871748",+ "digikey": "2156-TLC0834CDR-296-ND",+ "mouser": "595-TLC0834CDR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T17:04:13Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "2156-TLC0834CDR-296-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-TLC0834CDR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "2",+ "name": "CS",+ "type": "input",+ "description": "Chip select; set low to enable all logic circuits and hold low for the complete conversion, and a high level clears the internal registers and puts the outputs in high impedance."+ },+ {+ "number": "3",+ "name": "CH0",+ "type": "input",+ "description": "Analog multiplexer input channel 0, usable single-ended or as a differential pair with CH1, with input range -0.3 V to VCC + 0.3 V."+ },+ {+ "number": "4",+ "name": "CH1",+ "type": "input",+ "description": "Analog multiplexer input channel 1, usable single-ended or as a differential pair with CH0, with input range -0.3 V to VCC + 0.3 V."+ },+ {+ "number": "5",+ "name": "CH2",+ "type": "input",+ "description": "Analog multiplexer input channel 2, usable single-ended or as a differential pair with CH3, with input range -0.3 V to VCC + 0.3 V."+ },+ {+ "number": "6",+ "name": "CH3",+ "type": "input",+ "description": "Analog multiplexer input channel 3, usable single-ended or as a differential pair with CH2, with input range -0.3 V to VCC + 0.3 V."+ },+ {+ "number": "7",+ "name": "DGTL GND",+ "type": "power_in",+ "description": "Digital ground terminal, the reference for the network ground voltages."+ },+ {+ "number": "8",+ "name": "ANLG GND",+ "type": "power_in",+ "description": "Analog ground terminal."+ },+ {+ "number": "9",+ "name": "REF",+ "type": "input",+ "description": "Voltage reference input with 1.3 to 5.9 kΩ input resistance, adjustable to encode a smaller analog span to the full 8 bits (5 V reference typical)."+ },+ {+ "number": "10",+ "name": "DO",+ "type": "tri_state",+ "description": "Serial data output that shifts out the conversion result MSB first then LSB first, high-impedance when CS is high."+ },+ {+ "number": "11",+ "name": "SARS",+ "type": "tri_state",+ "description": "SAR status output that goes high while a conversion is in progress and low after eight clock periods, high-impedance when CS is high."+ },+ {+ "number": "12",+ "name": "CLK",+ "type": "input",+ "description": "Clock input from the processor with recommended frequency 10 kHz to 600 kHz and 40% to 60% duty cycle; DI is latched on each low-to-high transition."+ },+ {+ "number": "13",+ "name": "DI",+ "type": "input",+ "description": "Serial data input that shifts the start bit and multiplexer address word into the converter on CLK rising edges, with TTL/MOS-compatible levels (VIH 2 V min, VIL 0.8 V max)."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, 4.5 V to 5.5 V recommended (5 V nominal), 6.5 V absolute maximum."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet's text extraction of the TLC0834 D/N (SOIC/PDIP) pin diagram lists names in order with; Pin 1 is marked NC in the extracted text. Confirm against the printed TOP VIEW drawing that pin 1 is; The datasheet's 'TLC0834 . . . D OR N PACKAGE' is the only D-package pinout given. The 'PW' drawing "+ ],+ "pages_sent": 19,+ "cost_usd": 0.1045,+ "at": "2026-10-08T17:03:48"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlc0838",+ "pages": 19,+ "sha256": "7da8a03a60087fd9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tlc0834cdr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tlc0834cdr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "fd3e9132ad6ff49166052004a8f1e84659c29fdf65c1fe9b5f224b95ce5ca6bc",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}