component
TLC0831CP
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Texas Instruments Analog To Digital Converters (ADC), PDIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+44@@ -0,0 +1,44 @@+# TLC0831CP++**Texas Instruments** · Analog To Digital Converters (ADC) · PDIP-8++TLC0831CP from Texas Instruments, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CS | input | Chip select, active low: a conversion starts when CS goes low and CS must be held low for the complete conversion; when CS goes high, internal registers clear and DO returns to high impedance, with CS high pulse duration of at least 220 ns. |+| 2 | IN+ | input | Positive analog input, which is compared to IN- (or to ground in single-ended use with IN- grounded), with the common-mode input voltage specified from -0.05 V to VCC+0.05 V. |+| 3 | IN- | input | Negative analog input, and the digital output code is 0000 0000 when IN- is more positive than IN+. |+| 4 | GND | power_in | Network ground terminal, to which all voltages except differential voltages are referenced. |+| 5 | REF | input | Voltage reference input with input resistance of 1.3 kΩ min, 2.4 kΩ typ, 5.9 kΩ max, typically set equal to VCC for ratiometric operation. |+| 6 | DO | tri_state | Serial data output that delivers the conversion MSB first and is high impedance when CS is high, with MSB-first propagation delay after CLK↑ of 650 ns typ and 1500 ns max at 100 pF. |+| 7 | CLK | input | Serial clock input, with recommended clock frequency of 10 kHz to 600 kHz and clock duty cycle of 40% to 60%. |+| 8 | VCC | power_in | Supply voltage, recommended 4.5 V min, 5 V nom, 5.5 V max, with absolute maximum of 6.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | PDIP-8 |+| Category | Data Acquisition |+| Pins | 8 |++## CAD (KiCad official)++- Symbol: `TLC0831CP`+- Footprint: `Package_DIP:DIP-8_W7.62mm`+- 3D model: PDIP-8 (KiCad packages3D, STEP)+- 3D model files: `tlc0831cp-etched.step` / `tlc0831cp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tlc0831cp.step` / `tlc0831cp.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tlc0831) (21 pp, sha256 `0af85a1e9ea62978`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tlc0831cp-datasheet.pdf)
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when CS goes high, internal registers clear and DO returns to high impedance, with CS high pulse duration of at least 220 ns."+ },+ {+ "number": "2",+ "name": "IN+",+ "type": "input",+ "description": "Positive analog input, which is compared to IN- (or to ground in single-ended use with IN- grounded), with the common-mode input voltage specified from -0.05 V to VCC+0.05 V."+ },+ {+ "number": "3",+ "name": "IN–",+ "type": "input",+ "description": "Negative analog input, and the digital output code is 0000 0000 when IN- is more positive than IN+."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Network ground terminal, to which all voltages except differential voltages are referenced."+ },+ {+ "number": "5",+ "name": "REF",+ "type": "input",+ "description": "Voltage reference input with input resistance of 1.3 kΩ min, 2.4 kΩ typ, 5.9 kΩ max, typically set equal to VCC for ratiometric operation."+ },+ {+ "number": "6",+ "name": "DO",+ "type": "tri_state",+ "description": "Serial data output that delivers the conversion MSB first and is high impedance when CS is high, with MSB-first propagation delay after CLK↑ of 650 ns typ and 1500 ns max at 100 pF."+ },+ {+ "number": "7",+ "name": "CLK",+ "type": "input",+ "description": "Serial clock input, with recommended clock frequency of 10 kHz to 600 kHz and clock duty cycle of 40% to 60%."+ },+ {+ "number": "8",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, recommended 4.5 V min, 5 V nom, 5.5 V max, with absolute maximum of 6.5 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet pinout diagram is the same for the TLC0831CP/IP PDIP-8 variant, and the extracted text; Clock frequency range is given in the recommended operating conditions as 10 kHz to 600 kHz (the tab",+ "1/8 pins cited to the wrong page (name found elsewhere): ['4:GND@p5']"+ ],+ "pages_sent": 21,+ "cost_usd": 0.084,+ "at": "2026-10-08T14:37:34"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tlc0831",+ "pages": 21,+ "sha256": "0af85a1e9ea62978",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tlc0831cp.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "body on z = 0, through-hole leads below",+ "extents_mm": [+ 7.874,+ 9.27,+ 6.98+ ],+ "zmin_mm": -3.3,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4a377a56a8d9e9c0b86c095ef9ecc1869ac19e7f5069a3247b294250bf4f235d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tlc0831cp-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "body on z = 0, through-hole leads below",+ "extents_mm": [+ 7.874,+ 9.27,+ 6.98+ ],+ "zmin_mm": -3.3,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "ef9a71ddf7a8c79855206b3bcbc1251dfeda8fd5413525969e3de4358f7f5ad2",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}