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TL16C2550RHBR
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Texas Instruments UART, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+69@@ -0,0 +1,69 @@+# TL16C2550RHBR++**Texas Instruments** · UART · VQFN-32-EP(5x5)++TL16C2550RHBR from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | D6 | bidirectional | Data bus bit 6 for 8-bit parallel CPU interface. |+| 2 | D7 | bidirectional | Data bus bit 7 for 8-bit parallel CPU interface. |+| 3 | RXB | input | Serial receive data input for UART channel B. |+| 4 | RXA | input | Serial receive data input for UART channel A. |+| 5 | TXA | output | Serial transmit data output for UART channel A. |+| 6 | TXB | output | Serial transmit data output for UART channel B. |+| 7 | CSA | input | Active-low chip select for UART channel A enabling register access. |+| 8 | CSB | input | Active-low chip select for UART channel B enabling register access. |+| 9 | NC | unconnected | No internal connection. |+| 10 | XTAL1 | input | Crystal oscillator input or external clock input for frequencies 1 to 24 MHz. |+| 11 | XTAL2 | output | Crystal oscillator output or buffered external clock output. |+| 12 | IOW | input | Write input (active-low strobe) transfers data bus contents to internal register. |+| 13 | GND | power_in | Signal and power ground (0 V reference). |+| 14 | IOR | input | Read input (active-low strobe) loads internal register contents onto data bus. |+| 15 | RTSB | output | Active-low request to send output for channel B hardware flow control. |+| 16 | CTSB | input | Active-low clear to send input for channel B hardware flow control. |+| 17 | NC | unconnected | No internal connection. |+| 18 | A2 | input | Address select bit 2 for internal register address selection. |+| 19 | A1 | input | Address select bit 1 for internal register address selection. |+| 20 | A0 | input | Address select bit 0 for internal register address selection. |+| 21 | INTA | output | Active-high interrupt output for UART channel A. |+| 22 | INTB | output | Active-high interrupt output for UART channel B. |+| 23 | RTSA | output | Active-low request to send output for channel A hardware flow control. |+| 24 | RESET | input | Active-high reset input clears all registers and disables transmitter and receiver. |+| 25 | CTSA | input | Active-low clear to send input for channel A hardware flow control. |+| 26 | VCC | power_in | Power supply voltage (1.8 V to 5 V nominal). |+| 27 | D0 | bidirectional | Data bus bit 0 (least significant bit) for parallel CPU interface. |+| 28 | D1 | bidirectional | Data bus bit 1 for parallel CPU interface. |+| 29 | D2 | bidirectional | Data bus bit 2 for parallel CPU interface. |+| 30 | D3 | bidirectional | Data bus bit 3 for parallel CPU interface. |+| 31 | D4 | bidirectional | Data bus bit 4 for parallel CPU interface. |+| 32 | D5 | bidirectional | Data bus bit 5 for parallel CPU interface. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-32-EP(5x5) |+| Category | Communication Interface Chip/UART/485/232 |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `TL16C2550RHBR`+- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`+- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `tl16c2550rhbr-etched.step` / `tl16c2550rhbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tl16c2550rhbr.step` / `tl16c2550rhbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/tl16c2550) (49 pp, sha256 `27f2cc28a5ba3ac9`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tl16c2550rhbr-datasheet.pdf)
page.jsonadded+352@@ -0,0 +1,352 @@+{+ "slug": "tl16c2550rhbr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments UART, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "communication interface chip-uart-485-232",+ "tl16c2550rhbr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "tl16c2550rhbr.kicad_sym",+ "tl16c2550rhbr.kicad_mod",+ "tl16c2550rhbr.glb",+ "tl16c2550rhbr.step",+ "tl16c2550rhbr.lbr",+ "docs/hero.png",+ "docs/tl16c2550rhbr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "tl16c2550rhbr-hero.glb",+ "tl16c2550rhbr-hero.overlay.json"+ ],+ "component": {+ "mpn": "TL16C2550RHBR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Communication Interface Chip/UART/485/232",+ "subcategory": "UART",+ "datasheet": "https://www.ti.com/cn/lit/gpn/tl16c2550",+ "parts": {+ "symbol": "tl16c2550rhbr.kicad_sym",+ "footprint": "tl16c2550rhbr.kicad_mod",+ "model_3d": "tl16c2550rhbr-hero.glb",+ "model_3d_plain": "tl16c2550rhbr.glb",+ "model_3d_step": "tl16c2550rhbr-etched.step",+ "model_3d_step_plain": "tl16c2550rhbr.step",+ "lbr": "tl16c2550rhbr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2653222",+ "digikey": "TL16C2550RHBR-ND",+ "mouser": "595-TL16C2550RHBR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T01:27:24Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "TL16C2550RHBR-ND",+ "status": "found",+ "lifecycle": "Last Time Buy"+ },+ "mouser": {+ "pn": "595-TL16C2550RHBR",+ "status": "found",+ "lifecycle": "End of Life"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "D6",+ "type": "bidirectional",+ "description": "Data bus bit 6 for 8-bit parallel CPU interface."+ },+ {+ "number": "2",+ "name": "D7",+ "type": "bidirectional",+ "description": "Data bus bit 7 for 8-bit parallel CPU interface."+ },+ {+ "number": "3",+ "name": "RXB",+ "type": "input",+ "description": "Serial receive data input for UART channel B."+ },+ {+ "number": "4",+ "name": "RXA",+ "type": "input",+ "description": "Serial receive data input for UART channel A."+ },+ {+ "number": "5",+ "name": "TXA",+ "type": "output",+ "description": "Serial transmit data output for UART channel A."+ },+ {+ "number": "6",+ "name": "TXB",+ "type": "output",+ "description": "Serial transmit data output for UART channel B."+ },+ {+ "number": "7",+ "name": "CSA",+ "type": "input",+ "description": "Active-low chip select for UART channel A enabling register access."+ },+ {+ "number": "8",+ "name": "CSB",+ "type": "input",+ "description": "Active-low chip select for UART channel B enabling register access."+ },+ {+ "number": "9",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "10",+ "name": "XTAL1",+ "type": "input",+ "description": "Crystal oscillator input or external clock input for frequencies 1 to 24 MHz."+ },+ {+ "number": "11",+ "name": "XTAL2",+ "type": "output",+ "description": "Crystal oscillator output or buffered external clock output."+ },+ {+ "number": "12",+ "name": "IOW",+ "type": "input",+ "description": "Write input (active-low strobe) transfers data bus contents to internal register."+ },+ {+ "number": "13",+ "name": "GND",+ "type": "power_in",+ "description": "Signal and power ground (0 V reference)."+ },+ {+ "number": "14",+ "name": "IOR",+ "type": "input",+ "description": "Read input (active-low strobe) loads internal register contents onto data bus."+ },+ {+ "number": "15",+ "name": "RTSB",+ "type": "output",+ "description": "Active-low request to send output for channel B hardware flow control."+ },+ {+ "number": "16",+ "name": "CTSB",+ "type": "input",+ "description": "Active-low clear to send input for channel B hardware flow control."+ },+ {+ "number": "17",+ "name": "NC",+ "type": "unconnected",+ "description": "No internal connection."+ },+ {+ "number": "18",+ "name": "A2",+ "type": "input",+ "description": "Address select bit 2 for internal register address selection."+ },+ {+ "number": "19",+ "name": "A1",+ "type": "input",+ "description": "Address select bit 1 for internal register address selection."+ },+ {+ "number": "20",+ "name": "A0",+ "type": "input",+ "description": "Address select bit 0 for internal register address selection."+ },+ {+ "number": "21",+ "name": "INTA",+ "type": "output",+ "description": "Active-high interrupt output for UART channel A."+ },+ {+ "number": "22",+ "name": "INTB",+ "type": "output",+ "description": "Active-high interrupt output for UART channel B."+ },+ {+ "number": "23",+ "name": "RTSA",+ "type": "output",+ "description": "Active-low request to send output for channel A hardware flow control."+ },+ {+ "number": "24",+ "name": "RESET",+ "type": "input",+ "description": "Active-high reset input clears all registers and disables transmitter and receiver."+ },+ {+ "number": "25",+ "name": "CTSA",+ "type": "input",+ "description": "Active-low clear to send input for channel A hardware flow control."+ },+ {+ "number": "26",+ "name": "VCC",+ "type": "power_in",+ "description": "Power supply voltage (1.8 V to 5 V nominal)."+ },+ {+ "number": "27",+ "name": "D0",+ "type": "bidirectional",+ "description": "Data bus bit 0 (least significant bit) for parallel CPU interface."+ },+ {+ "number": "28",+ "name": "D1",+ "type": "bidirectional",+ "description": "Data bus bit 1 for parallel CPU interface."+ },+ {+ "number": "29",+ "name": "D2",+ "type": "bidirectional",+ "description": "Data bus bit 2 for parallel CPU interface."+ },+ {+ "number": "30",+ "name": "D3",+ "type": "bidirectional",+ "description": "Data bus bit 3 for parallel CPU interface."+ },+ {+ "number": "31",+ "name": "D4",+ "type": "bidirectional",+ "description": "Data bus bit 4 for parallel CPU interface."+ },+ {+ "number": "32",+ "name": "D5",+ "type": "bidirectional",+ "description": "Data bus bit 5 for parallel CPU interface."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pins 9 and 17 are not explicitly listed in PIN FUNCTIONS table for RHB package; inferred as NC based; RHB package omits 14 signals available in larger packages: DSRA, DSRB, RIA, RIB, CDA, CDB, OPA, OPB,",+ "exposed pad 33 added from the footprint"+ ],+ "pages_sent": 17,+ "cost_usd": 0.2525,+ "at": "2026-10-07T01:27:08"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/tl16c2550",+ "pages": 49,+ "sha256": "27f2cc28a5ba3ac9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "tl16c2550rhbr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.875+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "tl16c2550rhbr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 5,+ 5,+ 0.875+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4c4b7a336cff326131f2bf37a4bc336b47f587c61b85380a9ede5ac638719cfb",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}