TB67S279FTG

@@ -0,0 +1,89 @@+# TB67S279FTG++**TOSHIBA** · Stepper Motor Driver · VQFN-48-EP(7x7)++TB67S279FTG from TOSHIBA, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AGC0 | input | Active Gain Control setup pin No.0. Multi-state logic input (VCC, GND, VCC-100 kΩ pull-up, or GND-100 kΩ pull-down; ±20% resistor tolerance) that selects AGC operating mode together with AGC1. |+| 2 | AGC1 | input | Active Gain Control setup pin No.1. Multi-state logic input paired with AGC0 to configure AGC operating mode. |+| 3 | CLIM0 | input | AGC current limiter setup pin No.0. Multi-state input that, with CLIM1, sets the maximum motor current limit under AGC control. |+| 4 | CLIM1 | input | AGC current limiter setup pin No.1. Multi-state input paired with CLIM0 for AGC current limit selection. |+| 5 | FLIM | input | AGC frequency limiter setup pin. Multi-state input that programs the maximum AGC update frequency. |+| 6 | BOOST | input | AGC current boost setup pin. Multi-state input that enables/scales the transient current boost applied by AGC. |+| 7 | LTH | input | AGC threshold setup pin. Multi-state input that sets the AGC decision threshold. |+| 8 | GND | power_in | Signal/logic ground reference (0 V). Tie to the PCB ground plane; use a single-point external termination together with the other GND pins and thermal pad. |+| 9 | NC | unconnected | No connection. Leave open - do not connect any PCB trace. |+| 10 | VMA | power_in | Ach motor power supply input (VM, up to 50 V, 2.0 A). Bond both VMA pins together at the nearest point of the driver and decouple locally. |+| 11 | VMA | power_in | Ach motor power supply input (VM). Second VMA pad; must be shorted to pin 10 at the driver. |+| 12 | NC | unconnected | No connection. Leave open. |+| 13 | OUTA+ | output | Ach motor output (+). H-bridge output to motor coil A (positive terminal), 2.0 A max. Bond both OUTA+ pads together at the driver. |+| 14 | OUTA+ | output | Ach motor output (+). Second OUTA+ pad; must be tied to pin 13. |+| 15 | RSAGND | power_in | Ach motor power ground / sense return. Return path for the Ach H-bridge; ACDS senses current internally, no external sense resistor required. |+| 16 | RSAGND | power_in | Ach motor power ground / sense return. Second RSAGND pad; tie to pin 15 at the driver. |+| 17 | OUTA- | output | Ach motor output (-). H-bridge output to motor coil A (negative terminal), 2.0 A max. |+| 18 | OUTA- | output | Ach motor output (-). Second OUTA- pad; tie to pin 17. |+| 19 | OUTB- | output | Bch motor output (-). H-bridge output to motor coil B (negative terminal), 2.0 A max. |+| 20 | OUTB- | output | Bch motor output (-). Second OUTB- pad; tie to pin 19. |+| 21 | RSBGND | power_in | Bch motor power ground / sense return. Return path for the Bch H-bridge; ACDS provides sense-resistor-less current control. |+| 22 | RSBGND | power_in | Bch motor power ground / sense return. Second RSBGND pad; tie to pin 21. |+| 23 | OUTB+ | output | Bch motor output (+). H-bridge output to motor coil B (positive terminal), 2.0 A max. |+| 24 | OUTB+ | output | Bch motor output (+). Second OUTB+ pad; tie to pin 23. |+| 25 | NC | unconnected | No connection. Leave open. |+| 26 | VMB | power_in | Bch motor power supply input (VM, up to 50 V, 2.0 A). Tie both VMB pins together at the driver and decouple locally. |+| 27 | VMB | power_in | Bch motor power supply input (VM). Second VMB pad; must be shorted to pin 26. |+| 28 | NC | unconnected | No connection. Leave open. |+| 29 | GND | power_in | Signal/logic ground reference (0 V). Tie to the PCB ground plane at a single common point with other GND pins and the thermal pad. |+| 30 | GND | power_in | Signal/logic ground reference (0 V). |+| 31 | VREFB | input | Bch current threshold reference. Analog voltage input that sets the peak coil-B current threshold together with the internal ACDS. |+| 32 | VREFA | input | Ach current threshold reference. Analog voltage input that sets the peak coil-A current threshold. |+| 33 | VCC | power_out | Internal 5 V regulator voltage monitor pin. Bypass to GND with a local ceramic capacitor; not intended to source external loads. Tie both VCC pins together. |+| 34 | VCC | power_out | Internal 5 V regulator voltage monitor pin. Second VCC pad; must be tied to pin 33. |+| 35 | OSCM | bidirectional | Internal oscillator frequency monitor and setting pin. Connect an external RC network to program the constant-current PWM chopping frequency; can also be monitored to observe the internal oscillator. |+| 36 | NC | unconnected | No connection. Leave open. |+| 37 | NC | unconnected | No connection. Leave open. |+| 38 | NC | unconnected | No connection. Leave open. |+| 39 | DMODE0 | input | Step resolution setting pin No.0. Logic input (VIL ≤ 0.8 V, 2.0 V ≤ VIH ≤ 5.5 V). Combined with DMODE1/2 to select Full, Half-a, Half-b, 1/4, 1/8, 1/16, or 1/32 micro-stepping. |+| 40 | DMODE1 | input | Step resolution setting pin No.1. Logic input paired with DMODE0 and DMODE2 to select the micro-stepping resolution. |+| 41 | DMODE2 | input | Step resolution setting pin No.2. Logic input paired with DMODE0/1 to select the micro-stepping resolution. |+| 42 | CW/CCW | input | Rotation direction select. Logic input that sets the current direction / motor rotation sense (clockwise vs counter-clockwise). |+| 43 | CLK | input | Step clock input. Each rising edge advances the internal electrical angle by one micro-step (as selected by DMODE0..2). Logic-level input (VIL ≤ 0.8 V, VIH 2.0-5.5 V). |+| 44 | ENABLE | input | Motor output enable. Logic input that turns the H-bridge outputs ON/OFF (active-high enable). |+| 45 | RESET | input | Electrical-angle initialize input. Logic input; when asserted, resets the internal step counter/electrical angle to the initial state. |+| 46 | MO | output | Electrical-angle monitor output. Digital output that indicates when the internal electrical angle is at the reference (home) position - used by external logic to synchronize with the initial angle. |+| 47 | LO1 | output | Error flag output pin No.1. Open-drain-style status output that signals fault conditions (TSD/ISD/OPD/POR) in combination with LO2. |+| 48 | LO2 | output | Error flag output pin No.2. Status output paired with LO1 to encode which fault has been detected. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | TOSHIBA |+| Package | VQFN-48-EP(7x7) |+| Category | Motor Driver ICs |+| Pins | 48 |++## Ordering variants++Same part, different packaging or reel option.++- `TB67S279FTG`++## CAD (KiCad official)++- Symbol: `TB67S279FTG`+- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`+- 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [TOSHIBA datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588927815941574656) (None pp, sha256 `763c07ac64dd7f34`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tb67s279ftg-datasheet.pdf)