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Set visibility: public

Ray ·306e3b0e4c ·28d ago ·parent a13463d
1 file changed +7−4
page.json+7−4
@@ -32,7 +32,7 @@         "number": "1",         "name": "AGC0",         "type": "input",-        "description": "Active Gain Control setup pin No.0. Multi-state logic input (VCC, GND, VCC-100 k\u03a9 pull-up, or GND-100 k\u03a9 pull-down; \u00b120% resistor tolerance) that selects AGC operating mode together with AGC1."+        "description": "Active Gain Control setup pin No.0. Multi-state logic input (VCC, GND, VCC-100 kΩ pull-up, or GND-100 kΩ pull-down; ±20% resistor tolerance) that selects AGC operating mode together with AGC1."       },       {         "number": "2",@@ -260,7 +260,7 @@         "number": "39",         "name": "DMODE0",         "type": "input",-        "description": "Step resolution setting pin No.0. Logic input (VIL \u2264 0.8 V, 2.0 V \u2264 VIH \u2264 5.5 V). Combined with DMODE1/2 to select Full, Half-a, Half-b, 1/4, 1/8, 1/16, or 1/32 micro-stepping."+        "description": "Step resolution setting pin No.0. Logic input (VIL ≤ 0.8 V, 2.0 V ≤ VIH ≤ 5.5 V). Combined with DMODE1/2 to select Full, Half-a, Half-b, 1/4, 1/8, 1/16, or 1/32 micro-stepping."       },       {         "number": "40",@@ -284,7 +284,7 @@         "number": "43",         "name": "CLK",         "type": "input",-        "description": "Step clock input. Each rising edge advances the internal electrical angle by one micro-step (as selected by DMODE0..2). Logic-level input (VIL \u2264 0.8 V, VIH 2.0-5.5 V)."+        "description": "Step clock input. Each rising edge advances the internal electrical angle by one micro-step (as selected by DMODE0..2). Logic-level input (VIL ≤ 0.8 V, VIH 2.0-5.5 V)."       },       {         "number": "44",@@ -384,5 +384,8 @@     "docs/tb67s279ftg-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ]+  ],+  "visibility": {+    "public": true+  } }\ No newline at end of file