component
SY8120B1ABC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, SOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.md+14@@ -34,6 +34,20 @@ SY8120B1ABC from Silergy Corp, in a SOT-23-6. Pinout and pin descriptions extrac - Footprint: `Package_TO_SOT_SMD:SOT-23-6` - 3D model: SOT-23-6 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`sy8120b1abc.step`](sy8120b1abc.step) | 97 KB | You want the bare part, or you mark your own boards. |+| [`sy8120b1abc-etched.step`](sy8120b1abc-etched.step) | 2.3 MB | You want the part with `SY8120B1ABC` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 557 faces against 117 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1@@ -1,6 +1,6 @@ { "slug": "sy8120b1abc",- "version": "0.1.0",+ "version": "0.2.0", "type": "component", "description": "Silergy Corp DC-DC Converters, SOT-23-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "tags": [
page.json+11−11@@ -4,7 +4,7 @@ "slug": "sy8120b1abc", "title": "SY8120B1ABC", "brief": "Silergy Corp DC-DC Converters, SOT-23-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.2.0", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -34,37 +34,37 @@ "number": "1", "name": "BS", "type": "passive",- "description": "Boot-strap pin. Supplies the high-side gate driver via a bootstrap capacitor. Decouple to LX with a 0.1 \u00b5F ceramic capacitor. Absolute maximum BS-LX voltage is 4 V."+ "description": "Boot-strap pin. Supplies the high-side gate driver via a bootstrap capacitor. Decouple to LX with a 0.1 µF ceramic capacitor. Absolute maximum BS-LX voltage is 4 V." }, { "number": "2", "name": "GND", "type": "power_in",- "description": "Device ground. Also serves as the thermal case reference (\u03b8JC measured at this pin). Connect to a large PCB copper plane for best thermal and noise performance."+ "description": "Device ground. Also serves as the thermal case reference (θJC measured at this pin). Connect to a large PCB copper plane for best thermal and noise performance." }, { "number": "3", "name": "FB", "type": "input",- "description": "Output feedback pin. Connect to the center point of the external resistor divider to program VOUT via Vout = 0.6 \u00d7 (1 + R1/R2). Internal reference is 0.6 V \u00b12%; FB input current is \u00b150 nA max."+ "description": "Output feedback pin. Connect to the center point of the external resistor divider to program VOUT via Vout = 0.6 × (1 + R1/R2). Internal reference is 0.6 V ±2%; FB input current is ±50 nA max." }, { "number": "4", "name": "EN", "type": "input",- "description": "Enable control input. Pull high (\u22651.5 V) to turn the regulator on, pull below 0.4 V to shut down. Do not float; absolute maximum is VIN + 0.3 V. Consider a 1 M\u03a9 pull-down to GND if driven from a high-impedance source."+ "description": "Enable control input. Pull high (≥1.5 V) to turn the regulator on, pull below 0.4 V to shut down. Do not float; absolute maximum is VIN + 0.3 V. Consider a 1 MΩ pull-down to GND if driven from a high-impedance source." }, { "number": "5", "name": "IN", "type": "power_in",- "description": "Input supply pin. Operates from 4.5 V to 18 V (19 V absolute maximum). Decouple to GND with at least a 1 \u00b5F (4.7 \u00b5F recommended) low-ESR X5R ceramic capacitor placed close to the pin."+ "description": "Input supply pin. Operates from 4.5 V to 18 V (19 V absolute maximum). Decouple to GND with at least a 1 µF (4.7 µF recommended) low-ESR X5R ceramic capacitor placed close to the pin." }, { "number": "6", "name": "LX", "type": "power_out",- "description": "Switching node. Connect to the external output inductor. Internal top FET RDS(on) 130 m\u03a9, bottom FET 120 m\u03a9; peak current limit 3.6 A, valley current limit 2 A. Minimize PCB copper area on this net to reduce EMI."+ "description": "Switching node. Connect to the external output inductor. Internal top FET RDS(on) 130 mΩ, bottom FET 120 mΩ; peak current limit 3.6 A, valley current limit 2 A. Minimize PCB copper area on this net to reduce EMI." } ], "provenance": {@@ -138,9 +138,9 @@ "docs/hero.png", "docs/sy8120b1abc-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "Silergy Corp DC-DC Converters, SOT-23-6. Datasheet-verified pinout, KiCad symbol/footprint/3D." }