component
SY8089AAAC
Public Made by Adomby adom
Silergy Corp DC-DC Converters, SOT-23-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C78988). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+27−7
page.json+7−5@@ -26,13 +26,15 @@ "model_3d_step": "sy8089aaac.step", "lbr": "sy8089aaac.lbr" },- "distributor_links": {},+ "distributor_links": {+ "lcsc": "C78988"+ }, "pins": [ { "number": "1", "name": "EN", "type": "input",- "description": "Enable control input. Pull high (>1.5V) to turn on the regulator; pull low (<0.4V) to shut down (Ishdn ~0.1µA). Do not float; add a 1MΩ pull-down to GND if the driving source can go high-Z."+ "description": "Enable control input. Pull high (>1.5V) to turn on the regulator; pull low (<0.4V) to shut down (Ishdn ~0.1\u00b5A). Do not float; add a 1M\u03a9 pull-down to GND if the driving source can go high-Z." }, { "number": "2",@@ -44,19 +46,19 @@ "number": "3", "name": "LX", "type": "power_out",- "description": "Switching node output; connect to the external inductor (typ. 2.2µH). Internal PFET (110mΩ) sources to VIN and NFET (80mΩ) sinks to GND; peak current limit 3.5A. Minimize PCB copper area on this node to reduce switching noise."+ "description": "Switching node output; connect to the external inductor (typ. 2.2\u00b5H). Internal PFET (110m\u03a9) sources to VIN and NFET (80m\u03a9) sinks to GND; peak current limit 3.5A. Minimize PCB copper area on this node to reduce switching noise." }, { "number": "4", "name": "IN", "type": "power_in",- "description": "Supply input, 2.7V to 5.5V (abs max 6.0V). Decouple to GND with at least a 10µF (typ. 22µF) X5R/X7R ceramic capacitor placed close to the IN and GND pins."+ "description": "Supply input, 2.7V to 5.5V (abs max 6.0V). Decouple to GND with at least a 10\u00b5F (typ. 22\u00b5F) X5R/X7R ceramic capacitor placed close to the IN and GND pins." }, { "number": "5", "name": "FB", "type": "input",- "description": "Output voltage feedback input. Connect to the mid-point of the R1/R2 output divider to program Vout = 0.6V × (1 + R1/R2). Reference is 0.6V (±2%); IFB ±50nA. Keep FB trace away from the LX net."+ "description": "Output voltage feedback input. Connect to the mid-point of the R1/R2 output divider to program Vout = 0.6V \u00d7 (1 + R1/R2). Reference is 0.6V (\u00b12%); IFB \u00b150nA. Keep FB trace away from the LX net." } ], "provenance": {
sy8089aaac.lbr+20−2@@ -59,6 +59,18 @@ <smd name="3" x="-1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/> <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/> <smd name="5" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-1.4500" y="1.5100"/>+ <vertex x="-1.6900" y="1.8400"/>+ <vertex x="-1.2100" y="1.8400"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.4000" y="1.4500"/>+ <vertex x="0.8000" y="1.4500"/>+ <vertex x="0.8000" y="-1.4500"/>+ <vertex x="-0.8000" y="-1.4500"/>+ <vertex x="-0.8000" y="1.0500"/>+ </polygon> <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/> <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/> <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@ <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/> <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="SY8089AAAC">@@ -100,7 +112,13 @@ <connect gate="G$1" pin="FB" pad="5"/> <connect gate="G$1" pin="IN" pad="4"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="SY8089AAAC" constant="no"/>+ <attribute name="MANUFACTURER" value="Silergy Corp" constant="no"/>+ <attribute name="LCSC_PN" value="C78988" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>