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STM8S903F3P6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+56@@ -0,0 +1,56 @@+# STM8S903F3P6++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · TSSOP-20++STM8S903F3P6 from STMicroelectronics, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PD4 | bidirectional | Port D4 is a high-sink-capable I/O (O3 speed) whose default function is Timer 5 channel 1 or the BEEP output, with UART1 clock (UART1_CK) available through the AFR2 remap option. |+| 2 | PD5 | bidirectional | Port D5 is a high-sink-capable I/O (O3 speed) whose default functions are analog input 5 (AIN5) and UART1 data transmit (UART1_TX). |+| 3 | PD6 | bidirectional | Port D6 is a high-sink-capable I/O (O3 speed) whose default functions are analog input 6 (AIN6) and UART1 data receive (UART1_RX). |+| 4 | NRST | bidirectional | Reset pin whose main function is Reset, listed as I/O in the pin table; its electrical limits are given in Table 44 (NRST pin characteristics), which is not in the extracted text. |+| 5 | PA1 | bidirectional | Port A1 is an I/O whose default function is the resonator/crystal input OSCIN, and in Halt/Active-halt mode it is automatically set to input weak pull-up, cannot wake the device, and should be used only as an input if Halt/Active-halt is used. |+| 6 | PA2 | bidirectional | Port A2 is an I/O whose default function is the resonator/crystal output OSCOUT, with slow output speed (O1, up to 2 MHz). |+| 7 | VSS | power_in | Digital ground. |+| 8 | VCAP | power_out | 1.8 V regulator capacitor pin that connects to the external VCAP capacitor described in section 10.3.1. |+| 9 | VDD | power_in | Digital power supply, specified for a 2.95 to 5.5 V operating voltage in the features list. |+| 10 | PA3 | bidirectional | Port A3 is a high-sink-capable I/O whose default function is Timer 5 channel 3, with SPI master/slave select (AFR1) or UART1 data transmit (AFR1:0) available through remap options. |+| 11 | PB5 | bidirectional | Port B5 is a true open-drain I/O (no P-buffer, weak pull-up or protection diode to VDD) carrying I2C data, with Timer 1 break input (TIM1_BKIN) available through the AFR4 remap. |+| 12 | PB4 | bidirectional | Port B4 is a true open-drain I/O (no P-buffer, weak pull-up or protection diode to VDD) carrying I2C clock, with ADC external trigger (ADC_ETR) available through the AFR4 remap. |+| 13 | PC3 | bidirectional | Port C3 is a high-sink-capable I/O whose default function is Timer 1 channel 3, with top level interrupt (TLI, AFR3) and Timer 1 inverted channel 1 (AFR7) available through remap options. |+| 14 | PC4 | bidirectional | Port C4 is a high-sink-capable I/O whose default function is Timer 1 channel 4 or configurable clock output (CLK_CCO), with analog input 2 (AIN2, AFR2) and Timer 1 inverted channel 2 (AFR7) available through remap options. |+| 15 | PC5/SPI_SCK | bidirectional | Port C5 is a high-sink-capable I/O whose default function is SPI clock, with Timer 5 channel 1 available through the AFR0 remap. |+| 16 | PC6 | bidirectional | Port C6 is a high-sink-capable I/O whose default function is SPI master out/slave in, with Timer 1 channel 1 available through the AFR0 remap. |+| 17 | PC7 | bidirectional | Port C7 is a high-sink-capable I/O whose default function is SPI master in/slave out, with Timer 1 channel 2 available through the AFR0 remap. |+| 18 | PD1/SWIM | bidirectional | Port D1 is a high-sink-capable I/O (O4 speed) carrying the SWIM data interface; it is in input pull-up during reset and after internal reset release. |+| 19 | PD2 | bidirectional | Port D2 is a high-sink-capable I/O whose default function is analog input 3 (AIN3), with Timer 5 channel 3 available through the AFR1 remap. |+| 20 | PD3 | bidirectional | Port D3 is a high-sink-capable I/O whose default function is analog input 4 (AIN4), with Timer 5 channel 2 and ADC external trigger (ADC_ETR) listed as its other function. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | TSSOP-20 |+| Category | Embedded Processors & Controllers |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `STM8S903F3P6`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)+- 3D model files: `stm8s903f3p6-etched.step` / `stm8s903f3p6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8s903f3p6.step` / `stm8s903f3p6.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922932042584064) (124 pp, sha256 `76ef2064c8429253`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stm8s903f3p6-datasheet.pdf)
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its electrical limits are given in Table 44 (NRST pin characteristics), which is not in the extracted text."+ },+ {+ "number": "5",+ "name": "PA1",+ "type": "bidirectional",+ "description": "Port A1 is an I/O whose default function is the resonator/crystal input OSCIN, and in Halt/Active-halt mode it is automatically set to input weak pull-up, cannot wake the device, and should be used only as an input if Halt/Active-halt is used."+ },+ {+ "number": "6",+ "name": "PA2",+ "type": "bidirectional",+ "description": "Port A2 is an I/O whose default function is the resonator/crystal output OSCOUT, with slow output speed (O1, up to 2 MHz)."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "8",+ "name": "VCAP",+ "type": "power_out",+ "description": "1.8 V regulator capacitor pin that connects to the external VCAP capacitor described in section 10.3.1."+ },+ {+ "number": "9",+ "name": "VDD",+ "type": "power_in",+ "description": "Digital power supply, specified for a 2.95 to 5.5 V operating voltage in the features list."+ },+ {+ "number": "10",+ "name": "PA3",+ "type": "bidirectional",+ "description": "Port A3 is a high-sink-capable I/O whose default function is Timer 5 channel 3, with SPI master/slave select (AFR1) or UART1 data transmit (AFR1:0) available through remap options."+ },+ {+ "number": "11",+ "name": "PB5",+ "type": "bidirectional",+ "description": "Port B5 is a true open-drain I/O (no P-buffer, weak pull-up or protection diode to VDD) carrying I2C data, with Timer 1 break input (TIM1_BKIN) available through the AFR4 remap."+ },+ {+ "number": "12",+ "name": "PB4",+ "type": "bidirectional",+ "description": "Port B4 is a true open-drain I/O (no P-buffer, weak pull-up or protection diode to VDD) carrying I2C clock, with ADC external trigger (ADC_ETR) available through the AFR4 remap."+ },+ {+ "number": "13",+ "name": "PC3",+ "type": "bidirectional",+ "description": "Port C3 is a high-sink-capable I/O whose default function is Timer 1 channel 3, with top level interrupt (TLI, AFR3) and Timer 1 inverted channel 1 (AFR7) available through remap options."+ },+ {+ "number": "14",+ "name": "PC4",+ "type": "bidirectional",+ "description": "Port C4 is a high-sink-capable I/O whose default function is Timer 1 channel 4 or configurable clock output (CLK_CCO), with analog input 2 (AIN2, AFR2) and Timer 1 inverted channel 2 (AFR7) available through remap options."+ },+ {+ "number": "15",+ "name": "PC5/SPI_SCK",+ "type": "bidirectional",+ "description": "Port C5 is a high-sink-capable I/O whose default function is SPI clock, with Timer 5 channel 1 available through the AFR0 remap."+ },+ {+ "number": "16",+ "name": "PC6",+ "type": "bidirectional",+ "description": "Port C6 is a high-sink-capable I/O whose default function is SPI master out/slave in, with Timer 1 channel 1 available through the AFR0 remap."+ },+ {+ "number": "17",+ "name": "PC7",+ "type": "bidirectional",+ "description": "Port C7 is a high-sink-capable I/O whose default function is SPI master in/slave out, with Timer 1 channel 2 available through the AFR0 remap."+ },+ {+ "number": "18",+ "name": "PD1/SWIM",+ "type": "bidirectional",+ "description": "Port D1 is a high-sink-capable I/O (O4 speed) carrying the SWIM data interface; it is in input pull-up during reset and after internal reset release."+ },+ {+ "number": "19",+ "name": "PD2",+ "type": "bidirectional",+ "description": "Port D2 is a high-sink-capable I/O whose default function is analog input 3 (AIN3), with Timer 5 channel 3 available through the AFR1 remap."+ },+ {+ "number": "20",+ "name": "PD3",+ "type": "bidirectional",+ "description": "Port D3 is a high-sink-capable I/O whose default function is analog input 4 (AIN4), with Timer 5 channel 2 and ADC external trigger (ADC_ETR) listed as its other function."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: VCAP type set to power_out (1.8 V regulator output needing an external capacitor); the datasheet onl; NRST is listed as type I/O in the pin table and mapped to bidirectional; its electrical limits (Tabl; Pin rows for these pins are on the page 24 continuation of Table 5; source_page set to 24 accordingl"+ ],+ "pages_sent": 59,+ "cost_usd": 0.2246,+ "at": "2026-10-08T02:56:18"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922932042584064",+ "pages": 124,+ "sha256": "76ef2064c8429253",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "stm8s903f3p6.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "97339947f3a7196470ec2f1d9f9b92bb2fc2ab66ad53be0cf105192585ef3c9a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "stm8s903f3p6-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 6.5,+ 1.2+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "0b077fb6bee80cd1c426d4e2ad0f9f120b003fe2f28d4cd53c56636a6c9b96b8",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}