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STM8S207C8T3
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+84@@ -0,0 +1,84 @@+# STM8S207C8T3++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)++STM8S207C8T3 from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NRST | bidirectional | Reset pin (datasheet lists it as I/O); its electrical characteristics are given in section 10.3.7 (Reset pin characteristics). |+| 2 | PA1/OSCIN | bidirectional | Port A1 I/O, also the resonator/crystal oscillator input (OSCIN), with slow (O1, up to 2 MHz) output speed. |+| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O, also the resonator/crystal oscillator output (OSCOUT), with slow (O1, up to 2 MHz) output speed. |+| 4 | VSSIO_1 | power_in | I/O ground pin for the first group of I/O pins. |+| 5 | VSS | power_in | Digital ground. |+| 6 | VCAP | passive | 1.8 V regulator capacitor connection; the external VCAP capacitor requirements are given in section 10.3.1. |+| 7 | VDD | power_in | Digital power supply; the device operates from 2.95 V to 5.5 V. |+| 8 | VDDIO_1 | power_in | I/O power supply for the first group of I/O pins. |+| 9 | PA3/TIM2_CH3 | bidirectional | Port A3 I/O with default function Timer 2 channel 3 (TIM2_CH3); TIM3_CH1 is available after AFR1 remapping. |+| 10 | PA4/UART1_RX | bidirectional | Port A4 I/O, high sink capable, with UART1 receive; its default state is controlled by the ROM bootloader and it returns to floating before bootloader exit. |+| 11 | PA5/UART1_TX | bidirectional | Port A5 I/O, high sink capable, with UART1 transmit. |+| 12 | PA6/UART1_CK | bidirectional | Port A6 I/O, high sink capable, with UART1 synchronous clock. |+| 13 | VDDA | power_in | Analog power supply. |+| 14 | VSSA | power_in | Analog ground. |+| 15 | PB7/AIN7 | bidirectional | Port B7 I/O with ADC analog input 7. |+| 16 | PB6/AIN6 | bidirectional | Port B6 I/O with ADC analog input 6. |+| 17 | PB5/AIN5 | bidirectional | Port B5 I/O with ADC analog input 5; I2C_SDA is available after AFR6 remapping. |+| 18 | PB4/AIN4 | bidirectional | Port B4 I/O with ADC analog input 4; I2C_SCL is available after AFR6 remapping. |+| 19 | PB3/AIN3 | bidirectional | Port B3 I/O with ADC analog input 3; TIM1_ETR is available after AFR5 remapping. |+| 20 | PB2/AIN2 | bidirectional | Port B2 I/O with ADC analog input 2; TIM1_CH3N is available after AFR5 remapping. |+| 21 | PB1/AIN1 | bidirectional | Port B1 I/O with ADC analog input 1; TIM1_CH2N is available after AFR5 remapping. |+| 22 | PB0/AIN0 | bidirectional | Port B0 I/O with ADC analog input 0; TIM1_CH1N is available after AFR5 remapping. |+| 23 | PE7/AIN8 | bidirectional | Port E7 I/O with ADC analog input 8. |+| 24 | PE6/AIN9 | bidirectional | Port E6 I/O with ADC analog input 9. |+| 25 | PE5/SPI_NSS | bidirectional | Port E5 I/O with SPI master/slave select function. |+| 26 | PC1/TIM1_CH1 | bidirectional | Port C1 I/O, high sink capable, with Timer 1 channel 1. |+| 27 | PC2/TIM1_CH2 | bidirectional | Port C2 I/O, high sink capable, with Timer 1 channel 2. |+| 28 | PC3/TIM1_CH3 | bidirectional | Port C3 I/O, high sink capable, with Timer 1 channel 3. |+| 29 | PC4/TIM1_CH4 | bidirectional | Port C4 I/O, high sink capable, with Timer 1 channel 4. |+| 30 | PC5/SPI_SCK | bidirectional | Port C5 I/O, high sink capable, with SPI clock. |+| 31 | VSSIO_2 | power_in | I/O ground pin for the second group of I/O pins. |+| 32 | VDDIO_2 | power_in | I/O power supply for the second group of I/O pins. |+| 33 | PC6/SPI_MOSI | bidirectional | Port C6 I/O, high sink capable, with SPI master out / slave in. |+| 34 | PC7/SPI_MISO | bidirectional | Port C7 I/O, high sink capable, with SPI master in / slave out. |+| 35 | PG0/CAN_TX | bidirectional | Port G0 I/O with beCAN transmit; the beCAN interface is available on STM8S208xx devices only. |+| 36 | PG1/CAN_RX | bidirectional | Port G1 I/O with beCAN receive; the beCAN interface is available on STM8S208xx devices only. |+| 37 | PE3/TIM1_BKIN | bidirectional | Port E3 I/O with Timer 1 break input. |+| 38 | PE2/I2C_SDA | bidirectional | Port E2 true open-drain I/O (no P-buffer and no protection diode to VDD) carrying the I2C data line. |+| 39 | PE1/I2C_SCL | bidirectional | Port E1 true open-drain I/O (no P-buffer and no protection diode to VDD) carrying the I2C clock line. |+| 40 | PE0/CLK_CCO | bidirectional | Port E0 I/O, high sink capable, with configurable clock output (CLK_CCO). |+| 41 | PD0/TIM3_CH2 | bidirectional | Port D0 I/O, high sink capable, with Timer 3 channel 2; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are available after remapping. |+| 42 | PD1/SWIM | bidirectional | Port D1 I/O, high sink capable, used as the SWIM data interface; it is input pull-up during reset and after internal reset release. |+| 43 | PD2/TIM3_CH1 | bidirectional | Port D2 I/O, high sink capable, with Timer 3 channel 1; TIM2_CH3 is available after AFR1 remapping. |+| 44 | PD3/TIM2_CH2 | bidirectional | Port D3 I/O, high sink capable, with Timer 2 channel 2; ADC_ETR is available after AFR0 remapping. |+| 45 | PD4/TIM2_CH1/BEEP | bidirectional | Port D4 I/O, high sink capable, with Timer 2 channel 1; BEEP output is available after AFR7 remapping. |+| 46 | PD5/UART3_TX | bidirectional | Port D5 I/O with UART3 data transmit. |+| 47 | PD6/UART3_RX | bidirectional | Port D6 I/O with UART3 data receive; its default state is controlled by the ROM bootloader and it returns to floating before bootloader exit. |+| 48 | PD7/TLI | bidirectional | Port D7 I/O with top level interrupt input (TLI). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-48(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `STM8S207C8T3`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `stm8s207c8t3-etched.step` / `stm8s207c8t3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8s207c8t3.step` / `stm8s207c8t3.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923270871179264) (117 pp, sha256 `7adeaa849cf9e22f`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stm8s207c8t3-datasheet.pdf)
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its electrical characteristics are given in section 10.3.7 (Reset pin characteristics)."+ },+ {+ "number": "2",+ "name": "PA1/OSCIN",+ "type": "bidirectional",+ "description": "Port A1 I/O, also the resonator/crystal oscillator input (OSCIN), with slow (O1, up to 2 MHz) output speed."+ },+ {+ "number": "3",+ "name": "PA2/OSCOUT",+ "type": "bidirectional",+ "description": "Port A2 I/O, also the resonator/crystal oscillator output (OSCOUT), with slow (O1, up to 2 MHz) output speed."+ },+ {+ "number": "4",+ "name": "VSSIO_1",+ "type": "power_in",+ "description": "I/O ground pin for the first group of I/O pins."+ },+ {+ "number": "5",+ "name": "VSS",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "6",+ "name": "VCAP",+ "type": "passive",+ "description": "1.8 V regulator capacitor connection; the external VCAP capacitor requirements are given in section 10.3.1."+ },+ {+ "number": "7",+ "name": "VDD",+ "type": "power_in",+ "description": "Digital power supply; the device operates from 2.95 V to 5.5 V."+ },+ {+ "number": "8",+ "name": "VDDIO_1",+ "type": "power_in",+ "description": "I/O power supply for the first group of I/O pins."+ },+ {+ "number": "9",+ "name": "PA3/TIM2_CH3",+ "type": "bidirectional",+ "description": "Port A3 I/O with default function Timer 2 channel 3 (TIM2_CH3); TIM3_CH1 is available after AFR1 remapping."+ },+ {+ "number": "10",+ "name": "PA4/UART1_RX",+ "type": "bidirectional",+ "description": "Port A4 I/O, high sink capable, with UART1 receive; its default state is controlled by the ROM bootloader and it returns to floating before bootloader exit."+ },+ {+ "number": "11",+ "name": "PA5/UART1_TX",+ "type": "bidirectional",+ "description": "Port A5 I/O, high sink capable, with UART1 transmit."+ },+ {+ "number": "12",+ "name": "PA6/UART1_CK",+ "type": "bidirectional",+ "description": "Port A6 I/O, high sink capable, with UART1 synchronous clock."+ },+ {+ "number": "13",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power supply."+ },+ {+ "number": "14",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "15",+ "name": "PB7/AIN7",+ "type": "bidirectional",+ "description": "Port B7 I/O with ADC analog input 7."+ },+ {+ "number": "16",+ "name": "PB6/AIN6",+ "type": "bidirectional",+ "description": "Port B6 I/O with ADC analog input 6."+ },+ {+ "number": "17",+ "name": "PB5/AIN5",+ "type": "bidirectional",+ "description": "Port B5 I/O with ADC analog input 5; I2C_SDA is available after AFR6 remapping."+ },+ {+ "number": "18",+ "name": "PB4/AIN4",+ "type": "bidirectional",+ "description": "Port B4 I/O with ADC analog input 4; I2C_SCL is available after AFR6 remapping."+ },+ {+ "number": "19",+ "name": "PB3/AIN3",+ "type": "bidirectional",+ "description": "Port B3 I/O with ADC analog input 3; TIM1_ETR is available after AFR5 remapping."+ },+ {+ "number": "20",+ "name": "PB2/AIN2",+ "type": "bidirectional",+ "description": "Port B2 I/O with ADC analog input 2; TIM1_CH3N is available after AFR5 remapping."+ },+ {+ "number": "21",+ "name": "PB1/AIN1",+ "type": "bidirectional",+ "description": "Port B1 I/O with ADC analog input 1; TIM1_CH2N is available after AFR5 remapping."+ },+ {+ "number": "22",+ "name": "PB0/AIN0",+ "type": "bidirectional",+ "description": "Port B0 I/O with ADC analog input 0; TIM1_CH1N is available after AFR5 remapping."+ },+ {+ "number": "23",+ "name": "PE7/AIN8",+ "type": "bidirectional",+ "description": "Port E7 I/O with ADC analog input 8."+ },+ {+ "number": "24",+ "name": "PE6/AIN9",+ "type": "bidirectional",+ "description": "Port E6 I/O with ADC analog input 9."+ },+ {+ "number": "25",+ "name": "PE5/SPI_NSS",+ "type": "bidirectional",+ "description": "Port E5 I/O with SPI master/slave select function."+ },+ {+ "number": "26",+ "name": "PC1/TIM1_CH1",+ "type": "bidirectional",+ "description": "Port C1 I/O, high sink capable, with Timer 1 channel 1."+ },+ {+ "number": "27",+ "name": "PC2/TIM1_CH2",+ "type": "bidirectional",+ "description": "Port C2 I/O, high sink capable, with Timer 1 channel 2."+ },+ {+ "number": "28",+ "name": "PC3/TIM1_CH3",+ "type": "bidirectional",+ "description": "Port C3 I/O, high sink capable, with Timer 1 channel 3."+ },+ {+ "number": "29",+ "name": "PC4/TIM1_CH4",+ "type": "bidirectional",+ "description": "Port C4 I/O, high sink capable, with Timer 1 channel 4."+ },+ {+ "number": "30",+ "name": "PC5/SPI_SCK",+ "type": "bidirectional",+ "description": "Port C5 I/O, high sink capable, with SPI clock."+ },+ {+ "number": "31",+ "name": "VSSIO_2",+ "type": "power_in",+ "description": "I/O ground pin for the second group of I/O pins."+ },+ {+ "number": "32",+ "name": "VDDIO_2",+ "type": "power_in",+ "description": "I/O power supply for the second group of I/O pins."+ },+ {+ "number": "33",+ "name": "PC6/SPI_MOSI",+ "type": "bidirectional",+ "description": "Port C6 I/O, high sink capable, with SPI master out / slave in."+ },+ {+ "number": "34",+ "name": "PC7/SPI_MISO",+ "type": "bidirectional",+ "description": "Port C7 I/O, high sink capable, with SPI master in / slave out."+ },+ {+ "number": "35",+ "name": "PG0/CAN_TX",+ "type": "bidirectional",+ "description": "Port G0 I/O with beCAN transmit; the beCAN interface is available on STM8S208xx devices only."+ },+ {+ "number": "36",+ "name": "PG1/CAN_RX",+ "type": "bidirectional",+ "description": "Port G1 I/O with beCAN receive; the beCAN interface is available on STM8S208xx devices only."+ },+ {+ "number": "37",+ "name": "PE3/TIM1_BKIN",+ "type": "bidirectional",+ "description": "Port E3 I/O with Timer 1 break input."+ },+ {+ "number": "38",+ "name": "PE2/I2C_SDA",+ "type": "bidirectional",+ "description": "Port E2 true open-drain I/O (no P-buffer and no protection diode to VDD) carrying the I2C data line."+ },+ {+ "number": "39",+ "name": "PE1/I2C_SCL",+ "type": "bidirectional",+ "description": "Port E1 true open-drain I/O (no P-buffer and no protection diode to VDD) carrying the I2C clock line."+ },+ {+ "number": "40",+ "name": "PE0/CLK_CCO",+ "type": "bidirectional",+ "description": "Port E0 I/O, high sink capable, with configurable clock output (CLK_CCO)."+ },+ {+ "number": "41",+ "name": "PD0/TIM3_CH2",+ "type": "bidirectional",+ "description": "Port D0 I/O, high sink capable, with Timer 3 channel 2; TIM1_BKIN (AFR3) and CLK_CCO (AFR2) are available after remapping."+ },+ {+ "number": "42",+ "name": "PD1/SWIM",+ "type": "bidirectional",+ "description": "Port D1 I/O, high sink capable, used as the SWIM data interface; it is input pull-up during reset and after internal reset release."+ },+ {+ "number": "43",+ "name": "PD2/TIM3_CH1",+ "type": "bidirectional",+ "description": "Port D2 I/O, high sink capable, with Timer 3 channel 1; TIM2_CH3 is available after AFR1 remapping."+ },+ {+ "number": "44",+ "name": "PD3/TIM2_CH2",+ "type": "bidirectional",+ "description": "Port D3 I/O, high sink capable, with Timer 2 channel 2; ADC_ETR is available after AFR0 remapping."+ },+ {+ "number": "45",+ "name": "PD4/TIM2_CH1/BEEP",+ "type": "bidirectional",+ "description": "Port D4 I/O, high sink capable, with Timer 2 channel 1; BEEP output is available after AFR7 remapping."+ },+ {+ "number": "46",+ "name": "PD5/UART3_TX",+ "type": "bidirectional",+ "description": "Port D5 I/O with UART3 data transmit."+ },+ {+ "number": "47",+ "name": "PD6/UART3_RX",+ "type": "bidirectional",+ "description": "Port D6 I/O with UART3 data receive; its default state is controlled by the ROM bootloader and it returns to floating before bootloader exit."+ },+ {+ "number": "48",+ "name": "PD7/TLI",+ "type": "bidirectional",+ "description": "Port D7 I/O with top level interrupt input (TLI)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: MPN STM8S207C8T3 is in the STM8S207 family, but PG0/CAN_TX (pin 35) and PG1/CAN_RX (pin 36) are mark; Package LQFP48 7x7 mm was selected from the MPN (C = 48 pins, T = LQFP) and the datasheet LQFP48 col; Pin types are taken from the datasheet I/O column and mapped to KiCad classes: all port pins are bid"+ ],+ "pages_sent": 48,+ "cost_usd": 0.2267,+ "at": "2026-10-08T18:27:20"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588923270871179264",+ "pages": 117,+ "sha256": "7adeaa849cf9e22f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "stm8s207c8t3.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "stm8s207c8t3-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3eec636df2bd0894b7f5145ed0fede078faeb51c34e091a4eca8f2670154a61c",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}