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STM8S105S6T3C
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+80@@ -0,0 +1,80 @@+# STM8S105S6T3C++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)++STM8S105S6T3C from STMicroelectronics, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NRST | bidirectional | Reset pin (main function reset) with I/O type and weak pull-up (wpu) as listed in the pin description table. |+| 2 | PA1/OSCIN | bidirectional | Port A1 I/O (slow O1 output, weak pull-up and floating input options, external interrupt) with alternate function resonator/crystal input OSCIN. |+| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O (slow O1 output, weak pull-up and floating input options, external interrupt) with alternate function resonator/crystal output OSCOUT. |+| 4 | VSSIO_1 | power_in | I/O ground. |+| 5 | VSS | power_in | Digital ground. |+| 6 | VCAP | passive | 1.8 V regulator capacitor connection. |+| 7 | VDD | power_in | Digital power supply. |+| 8 | VDDIO_1 | power_in | I/O power supply. |+| 9 | PA4 | bidirectional | Port A4 I/O with high sink capability, fast/slow programmable output speed (O3), weak pull-up and floating input options, and external interrupt. |+| 10 | PA5 | bidirectional | Port A5 I/O with high sink capability, fast/slow programmable output speed (O3), weak pull-up and floating input options, and external interrupt. |+| 11 | PA6 | bidirectional | Port A6 I/O with high sink capability, fast/slow programmable output speed (O3), weak pull-up and floating input options, and external interrupt. |+| 12 | VDDA | power_in | Analog power supply. |+| 13 | VSSA | power_in | Analog ground. |+| 14 | PB7/AIN7 | bidirectional | Port B7 I/O with analog input 7 for the ADC, slow O1 output, weak pull-up and floating input options, and external interrupt. |+| 15 | PB6/AIN6 | bidirectional | Port B6 I/O with analog input 6 for the ADC, slow O1 output, weak pull-up and floating input options, and external interrupt. |+| 16 | PB5/AIN5/I2C_SDA | bidirectional | Port B5 I/O with analog input 5 for the ADC; alternate function I2C_SDA is available when option AFR6 is set. |+| 17 | PB4/AIN4/I2C_SCL | bidirectional | Port B4 I/O with analog input 4 for the ADC; alternate function I2C_SCL is available when option AFR6 is set. |+| 18 | PB3/AIN3/TIM1_ETR | bidirectional | Port B3 I/O with analog input 3 for the ADC; alternate function TIM1_ETR is available when option AFR5 is set. |+| 19 | PB2/AIN2/TIM1_CH3N | bidirectional | Port B2 I/O with analog input 2 for the ADC; alternate function TIM1_CH3N is available when option AFR5 is set. |+| 20 | PB1/AIN1/TIM1_CH2N | bidirectional | Port B1 I/O with analog input 1 for the ADC; alternate function TIM1_CH2N is available when option AFR5 is set. |+| 21 | PB0/AIN0/TIM1_CH1N | bidirectional | Port B0 I/O with analog input 0 for the ADC; alternate function TIM1_CH1N is available when option AFR5 is set. |+| 22 | PE6/AIN9 | bidirectional | Port E6 I/O with analog input 9; in the 44-pin package AIN9 cannot be used in ADC scan mode. |+| 23 | PE5/SPI_NSS | bidirectional | Port E5 I/O with alternate function SPI master/slave select (NSS) and external interrupt. |+| 24 | PC1/TIM1_CH1/UART2_CK | bidirectional | Port C1 I/O with high sink capability and fast/slow programmable speed (O3); alternate functions are TIM1_CH1 and the UART2 synchronous clock UART2_CK. |+| 25 | PC2/TIM1_CH2 | bidirectional | Port C2 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is TIM1_CH2. |+| 26 | PC3/TIM1_CH3 | bidirectional | Port C3 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is TIM1_CH3. |+| 27 | PC5/SPI_SCK | bidirectional | Port C5 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is the SPI clock SPI_SCK. |+| 28 | VSSIO_2 | power_in | I/O ground. |+| 29 | VDDIO_2 | power_in | I/O power supply. |+| 30 | PC6/SPI_MOSI | bidirectional | Port C6 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is SPI master out / slave in (SPI_MOSI). |+| 31 | PC7/SPI_MISO | bidirectional | Port C7 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is SPI master in / slave out (SPI_MISO). |+| 32 | PG0 | bidirectional | Port G0 I/O with slow O1 output, weak pull-up and floating input options, and external interrupt; no alternate function listed. |+| 33 | PG1 | bidirectional | Port G1 I/O with slow O1 output, weak pull-up and floating input options, and external interrupt; no alternate function listed. |+| 34 | PE2/I2C_SDA | bidirectional | Port E2 I/O configured as a true open-drain pin (no P-buffer, weak pull-up or protection diode to VDD) carrying the I2C data line I2C_SDA. |+| 35 | PE1/I2C_SCL | bidirectional | Port E1 I/O configured as a true open-drain pin (no P-buffer, weak pull-up or protection diode to VDD) carrying the I2C clock line I2C_SCL. |+| 36 | PE0/CLK_CCO | bidirectional | Port E0 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is the configurable clock output CLK_CCO. |+| 37 | PD0/TIM3_CH2/TIM1_BKIN/CLK_CCO | bidirectional | Port D0 I/O with high sink capability; alternate function TIM3_CH2 by default, with TIM1_BKIN (option AFR3) or CLK_CCO (option AFR2) after remapping, where AFR2 takes priority over AFR3. |+| 38 | PD1/SWIM | bidirectional | Port D1 I/O with high sink capability and fast/slow programmable speed (O4), used as the SWIM single-wire debug data interface; the pin is input pull-up during reset and after internal reset release. |+| 39 | PD2/TIM3_CH1/TIM2_CH3 | bidirectional | Port D2 I/O with high sink capability and fast/slow programmable speed (O3); alternate function TIM3_CH1 by default, with TIM2_CH3 available after option AFR1 remapping. |+| 40 | PD3/TIM2_CH2/ADC_ETR | bidirectional | Port D3 I/O with high sink capability and fast/slow programmable speed (O3); alternate function TIM2_CH2 by default, with ADC_ETR available after option AFR0 remapping. |+| 41 | PD4/TIM2_CH1/BEEP | bidirectional | Port D4 I/O with high sink capability and fast/slow programmable speed (O3); alternate function TIM2_CH1 by default, with the BEEP output available after option AFR7 remapping. |+| 42 | PD5/UART2_TX | bidirectional | Port D5 I/O with slow O1 output, weak pull-up and floating input options, and external interrupt; alternate function is the UART2 data transmit output UART2_TX. |+| 43 | PD6/UART2_RX | bidirectional | Port D6 I/O with slow O1 output, weak pull-up and floating input options, and external interrupt; alternate function is the UART2 data receive input UART2_RX. |+| 44 | PD7/TLI/TIM1_CH4 | bidirectional | Port D7 I/O with slow O1 output, weak pull-up and floating input options, and external interrupt; alternate function is the top level interrupt input TLI, with TIM1_CH4 available after option AFR4 remapping. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-44(10x10) |+| Category | Embedded Processors & Controllers |+| Pins | 44 |++## CAD (KiCad official)++- Symbol: `STM8S105S6T3C`+- Footprint: `Package_QFP:LQFP-44_10x10mm_P0.8mm`+- 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)+- 3D model files: `stm8s105s6t3c-etched.step` / `stm8s105s6t3c-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8s105s6t3c.step` / `stm8s105s6t3c.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922896231751680) (121 pp, sha256 `b1007bc27bb78327`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stm8s105s6t3c-datasheet.pdf)
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alternate function I2C_SDA is available when option AFR6 is set."+ },+ {+ "number": "17",+ "name": "PB4/AIN4/I2C_SCL",+ "type": "bidirectional",+ "description": "Port B4 I/O with analog input 4 for the ADC; alternate function I2C_SCL is available when option AFR6 is set."+ },+ {+ "number": "18",+ "name": "PB3/AIN3/TIM1_ETR",+ "type": "bidirectional",+ "description": "Port B3 I/O with analog input 3 for the ADC; alternate function TIM1_ETR is available when option AFR5 is set."+ },+ {+ "number": "19",+ "name": "PB2/AIN2/TIM1_CH3N",+ "type": "bidirectional",+ "description": "Port B2 I/O with analog input 2 for the ADC; alternate function TIM1_CH3N is available when option AFR5 is set."+ },+ {+ "number": "20",+ "name": "PB1/AIN1/TIM1_CH2N",+ "type": "bidirectional",+ "description": "Port B1 I/O with analog input 1 for the ADC; alternate function TIM1_CH2N is available when option AFR5 is set."+ },+ {+ "number": "21",+ "name": "PB0/AIN0/TIM1_CH1N",+ "type": "bidirectional",+ "description": "Port B0 I/O with analog input 0 for the ADC; alternate function TIM1_CH1N is available when option AFR5 is set."+ },+ {+ "number": "22",+ "name": "PE6/AIN9",+ "type": "bidirectional",+ "description": "Port E6 I/O with analog input 9; in the 44-pin package AIN9 cannot be used in ADC scan mode."+ },+ {+ "number": "23",+ "name": "PE5/SPI_NSS",+ "type": "bidirectional",+ "description": "Port E5 I/O with alternate function SPI master/slave select (NSS) and external interrupt."+ },+ {+ "number": "24",+ "name": "PC1/TIM1_CH1/UART2_CK",+ "type": "bidirectional",+ "description": "Port C1 I/O with high sink capability and fast/slow programmable speed (O3); alternate functions are TIM1_CH1 and the UART2 synchronous clock UART2_CK."+ },+ {+ "number": "25",+ "name": "PC2/TIM1_CH2",+ "type": "bidirectional",+ "description": "Port C2 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is TIM1_CH2."+ },+ {+ "number": "26",+ "name": "PC3/TIM1_CH3",+ "type": "bidirectional",+ "description": "Port C3 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is TIM1_CH3."+ },+ {+ "number": "27",+ "name": "PC5/SPI_SCK",+ "type": "bidirectional",+ "description": "Port C5 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is the SPI clock SPI_SCK."+ },+ {+ "number": "28",+ "name": "VSSIO_2",+ "type": "power_in",+ "description": "I/O ground."+ },+ {+ "number": "29",+ "name": "VDDIO_2",+ "type": "power_in",+ "description": "I/O power supply."+ },+ {+ "number": "30",+ "name": "PC6/SPI_MOSI",+ "type": "bidirectional",+ "description": "Port C6 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is SPI master out / slave in (SPI_MOSI)."+ },+ {+ "number": "31",+ "name": "PC7/SPI_MISO",+ "type": "bidirectional",+ "description": "Port C7 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is SPI master in / slave out (SPI_MISO)."+ },+ {+ "number": "32",+ "name": "PG0",+ "type": "bidirectional",+ "description": "Port G0 I/O with slow O1 output, weak pull-up and floating input options, and external interrupt; no alternate function listed."+ },+ {+ "number": "33",+ "name": "PG1",+ "type": "bidirectional",+ "description": "Port G1 I/O with slow O1 output, weak pull-up and floating input options, and external interrupt; no alternate function listed."+ },+ {+ "number": "34",+ "name": "PE2/I2C_SDA",+ "type": "bidirectional",+ "description": "Port E2 I/O configured as a true open-drain pin (no P-buffer, weak pull-up or protection diode to VDD) carrying the I2C data line I2C_SDA."+ },+ {+ "number": "35",+ "name": "PE1/I2C_SCL",+ "type": "bidirectional",+ "description": "Port E1 I/O configured as a true open-drain pin (no P-buffer, weak pull-up or protection diode to VDD) carrying the I2C clock line I2C_SCL."+ },+ {+ "number": "36",+ "name": "PE0/CLK_CCO",+ "type": "bidirectional",+ "description": "Port E0 I/O with high sink capability and fast/slow programmable speed (O3); alternate function is the configurable clock output CLK_CCO."+ },+ {+ "number": "37",+ "name": "PD0/TIM3_CH2/TIM1_BKIN/CLK_CCO",+ "type": "bidirectional",+ "description": "Port D0 I/O with high sink capability; alternate function TIM3_CH2 by default, with TIM1_BKIN (option AFR3) or CLK_CCO (option AFR2) after remapping, where AFR2 takes priority over AFR3."+ },+ {+ "number": "38",+ "name": "PD1/SWIM",+ "type": "bidirectional",+ "description": "Port D1 I/O with high sink capability and fast/slow programmable speed (O4), used as the SWIM single-wire debug data interface; the pin is input pull-up during reset and after internal reset release."+ },+ {+ "number": "39",+ "name": "PD2/TIM3_CH1/TIM2_CH3",+ "type": "bidirectional",+ "description": "Port D2 I/O with high sink capability and fast/slow programmable speed (O3); alternate function TIM3_CH1 by default, with TIM2_CH3 available after option AFR1 remapping."+ },+ {+ "number": "40",+ "name": "PD3/TIM2_CH2/ADC_ETR",+ "type": "bidirectional",+ "description": "Port D3 I/O with high sink capability and fast/slow programmable speed (O3); alternate function TIM2_CH2 by default, with ADC_ETR available after option AFR0 remapping."+ },+ {+ "number": "41",+ "name": "PD4/TIM2_CH1/BEEP",+ "type": "bidirectional",+ "description": "Port D4 I/O with high sink capability and fast/slow programmable speed (O3); alternate function TIM2_CH1 by default, with the BEEP output available after option AFR7 remapping."+ },+ {+ "number": "42",+ "name": "PD5/UART2_TX",+ "type": "bidirectional",+ "description": "Port D5 I/O with slow O1 output, weak pull-up and floating input options, and external interrupt; alternate function is the UART2 data transmit output UART2_TX."+ },+ {+ "number": "43",+ "name": "PD6/UART2_RX",+ "type": "bidirectional",+ "description": "Port D6 I/O with slow O1 output, weak pull-up and floating input options, and external interrupt; alternate function is the UART2 data receive input UART2_RX."+ },+ {+ "number": "44",+ "name": "PD7/TLI/TIM1_CH4",+ "type": "bidirectional",+ "description": "Port D7 I/O with slow O1 output, weak pull-up and floating input options, and external interrupt; alternate function is the top level interrupt input TLI, with TIM1_CH4 available after option AFR4 remapping."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package selection: MPN STM8S105S6T3C decodes as S = 44-pin, 6 = 32 Kbyte Flash, T = LQFP, 3 = -40 to; Pins 1-44 all assigned: the datasheet's LQFP44 column in Table 5 contains exactly 44 entries. Pins n; Type judgement: NRST is listed as I/O in Table 5 and was classed as bidirectional; VCAP is a regulat"+ ],+ "pages_sent": 55,+ "cost_usd": 0.2237,+ "at": "2026-10-08T01:17:54"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922896231751680",+ "pages": 121,+ "sha256": "b1007bc27bb78327",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 44,+ "described": 44,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "stm8s105s6t3c.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "81aae6270b5c742bed79a8a35e9adf7fbed97c42e341e6b25ab20c1783b93b5d",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "stm8s105s6t3c-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "be707b1bf63ac752a29c988ad856cea3722061e90258783b0f826d5bc13f70b7",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}