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STM8S105K4T3C
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+68@@ -0,0 +1,68 @@+# STM8S105K4T3C++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)++STM8S105K4T3C from STMicroelectronics, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NRST | bidirectional | Device reset pin (listed as I/O in the pin table), with its characteristics given in the NRST pin characteristics section. |+| 2 | PA1/OSCIN | bidirectional | Port A1 I/O that also serves as the resonator/crystal input OSCIN, or the external clock signal input when option bit EXTCLK is set to 1. |+| 3 | PA2/OSCOUT | bidirectional | Port A2 I/O that also serves as the resonator/crystal output OSCOUT for the external crystal connected to OSCIN/OSCOUT. |+| 4 | VSS | power_in | Digital ground. |+| 5 | VCAP | passive | Connection for the 1.8 V internal regulator capacitor. |+| 6 | VDD | power_in | Digital power supply; the device operates from 2.95 V to 5.5 V. |+| 7 | VDDIO_1 | power_in | I/O power supply. |+| 8 | PF4/AIN12 | bidirectional | Port F4 I/O with analog input AIN12, which is not selectable in ADC scan mode or with the analog watchdog; a pull-up is applied during reset and the pin is input floating after reset release. |+| 9 | VDDA | power_in | Analog power supply. |+| 10 | VSSA | power_in | Analog ground. |+| 11 | PB5/AIN5 | bidirectional | Port B5 I/O with analog input AIN5; when option AFR6 is set, this pin becomes the I2C_SDA alternate function. |+| 12 | PB4/AIN4 | bidirectional | Port B4 I/O with analog input AIN4; when option AFR6 is set, this pin becomes the I2C_SCL alternate function. |+| 13 | PB3/AIN3 | bidirectional | Port B3 I/O with analog input AIN3; when option AFR5 is set, this pin becomes the TIM1_ETR alternate function. |+| 14 | PB2/AIN2 | bidirectional | Port B2 I/O with analog input AIN2; when option AFR5 is set, this pin becomes the TIM1_CH3N alternate function. |+| 15 | PB1/AIN1 | bidirectional | Port B1 I/O with analog input AIN1; when option AFR5 is set, this pin becomes the TIM1_CH2N alternate function. |+| 16 | PB0/AIN0 | bidirectional | Port B0 I/O with analog input AIN0; when option AFR5 is set, this pin becomes the TIM1_CH1N alternate function. |+| 17 | PE5/SPI_NSS | bidirectional | Port E5 I/O that serves as the SPI master/slave select input SPI_NSS. |+| 18 | PC1/TIM1_CH1/UART2_CK | bidirectional | Port C1 high sink I/O that serves as TIM1 channel 1 or the UART2 synchronous clock output UART2_CK. |+| 19 | PC2/TIM1_CH2 | bidirectional | Port C2 high sink I/O that serves as TIM1 channel 2. |+| 20 | PC3/TIM1_CH3 | bidirectional | Port C3 high sink I/O that serves as TIM1 channel 3. |+| 21 | PC4/TIM1_CH4 | bidirectional | Port C4 high sink I/O that serves as TIM1 channel 4. |+| 22 | PC5/SPI_SCK | bidirectional | Port C5 high sink I/O that serves as the SPI clock SPI_SCK. |+| 23 | PC6/SPI_MOSI | bidirectional | Port C6 high sink I/O that serves as the SPI master out / slave in line SPI_MOSI. |+| 24 | PC7/SPI_MISO | bidirectional | Port C7 high sink I/O that serves as the SPI master in / slave out line SPI_MISO. |+| 25 | PD0/TIM3_CH2 | bidirectional | Port D0 high sink I/O that serves as TIM3 channel 2; option AFR3 remaps it to TIM1_BKIN and option AFR2 remaps it to CLK_CCO (AFR2 has priority). |+| 26 | PD1/SWIM | bidirectional | Port D1 high sink I/O that serves as the SWIM single-wire data interface; the pin is in input pull-up during reset and after internal reset release. |+| 27 | PD2/TIM3_CH1 | bidirectional | Port D2 high sink I/O that serves as TIM3 channel 1; option AFR1 remaps it to TIM2_CH3. |+| 28 | PD3/TIM2_CH2 | bidirectional | Port D3 high sink I/O that serves as TIM2 channel 2; option AFR0 remaps it to the ADC_ETR input. |+| 29 | PD4/TIM2_CH1 | bidirectional | Port D4 high sink I/O that serves as TIM2 channel 1; option AFR7 makes it the BEEP output. |+| 30 | PD5/UART2_TX | bidirectional | Port D5 I/O that serves as the UART2 data transmit output UART2_TX. |+| 31 | PD6/UART2_RX | bidirectional | Port D6 I/O that serves as the UART2 data receive input UART2_RX. |+| 32 | PD7/TLI | bidirectional | Port D7 I/O that serves as the top level interrupt input TLI; option AFR4 remaps it to TIM1_CH4. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-32(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 32 |++## CAD (KiCad official)++- Symbol: `STM8S105K4T3C`+- Footprint: `Package_QFP:LQFP-32_7x7mm_P0.8mm`+- 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)+- 3D model files: `stm8s105k4t3c-etched.step` / `stm8s105k4t3c-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm8s105k4t3c.step` / `stm8s105k4t3c.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588924061560397824) (121 pp, sha256 `b1007bc27bb78327`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stm8s105k4t3c-datasheet.pdf)
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the device operates from 2.95 V to 5.5 V."+ },+ {+ "number": "7",+ "name": "VDDIO_1",+ "type": "power_in",+ "description": "I/O power supply."+ },+ {+ "number": "8",+ "name": "PF4/AIN12",+ "type": "bidirectional",+ "description": "Port F4 I/O with analog input AIN12, which is not selectable in ADC scan mode or with the analog watchdog; a pull-up is applied during reset and the pin is input floating after reset release."+ },+ {+ "number": "9",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power supply."+ },+ {+ "number": "10",+ "name": "VSSA",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "11",+ "name": "PB5/AIN5",+ "type": "bidirectional",+ "description": "Port B5 I/O with analog input AIN5; when option AFR6 is set, this pin becomes the I2C_SDA alternate function."+ },+ {+ "number": "12",+ "name": "PB4/AIN4",+ "type": "bidirectional",+ "description": "Port B4 I/O with analog input AIN4; when option AFR6 is set, this pin becomes the I2C_SCL alternate function."+ },+ {+ "number": "13",+ "name": "PB3/AIN3",+ "type": "bidirectional",+ "description": "Port B3 I/O with analog input AIN3; when option AFR5 is set, this pin becomes the TIM1_ETR alternate function."+ },+ {+ "number": "14",+ "name": "PB2/AIN2",+ "type": "bidirectional",+ "description": "Port B2 I/O with analog input AIN2; when option AFR5 is set, this pin becomes the TIM1_CH3N alternate function."+ },+ {+ "number": "15",+ "name": "PB1/AIN1",+ "type": "bidirectional",+ "description": "Port B1 I/O with analog input AIN1; when option AFR5 is set, this pin becomes the TIM1_CH2N alternate function."+ },+ {+ "number": "16",+ "name": "PB0/AIN0",+ "type": "bidirectional",+ "description": "Port B0 I/O with analog input AIN0; when option AFR5 is set, this pin becomes the TIM1_CH1N alternate function."+ },+ {+ "number": "17",+ "name": "PE5/SPI_NSS",+ "type": "bidirectional",+ "description": "Port E5 I/O that serves as the SPI master/slave select input SPI_NSS."+ },+ {+ "number": "18",+ "name": "PC1/TIM1_CH1/UART2_CK",+ "type": "bidirectional",+ "description": "Port C1 high sink I/O that serves as TIM1 channel 1 or the UART2 synchronous clock output UART2_CK."+ },+ {+ "number": "19",+ "name": "PC2/TIM1_CH2",+ "type": "bidirectional",+ "description": "Port C2 high sink I/O that serves as TIM1 channel 2."+ },+ {+ "number": "20",+ "name": "PC3/TIM1_CH3",+ "type": "bidirectional",+ "description": "Port C3 high sink I/O that serves as TIM1 channel 3."+ },+ {+ "number": "21",+ "name": "PC4/TIM1_CH4",+ "type": "bidirectional",+ "description": "Port C4 high sink I/O that serves as TIM1 channel 4."+ },+ {+ "number": "22",+ "name": "PC5/SPI_SCK",+ "type": "bidirectional",+ "description": "Port C5 high sink I/O that serves as the SPI clock SPI_SCK."+ },+ {+ "number": "23",+ "name": "PC6/SPI_MOSI",+ "type": "bidirectional",+ "description": "Port C6 high sink I/O that serves as the SPI master out / slave in line SPI_MOSI."+ },+ {+ "number": "24",+ "name": "PC7/SPI_MISO",+ "type": "bidirectional",+ "description": "Port C7 high sink I/O that serves as the SPI master in / slave out line SPI_MISO."+ },+ {+ "number": "25",+ "name": "PD0/TIM3_CH2",+ "type": "bidirectional",+ "description": "Port D0 high sink I/O that serves as TIM3 channel 2; option AFR3 remaps it to TIM1_BKIN and option AFR2 remaps it to CLK_CCO (AFR2 has priority)."+ },+ {+ "number": "26",+ "name": "PD1/SWIM",+ "type": "bidirectional",+ "description": "Port D1 high sink I/O that serves as the SWIM single-wire data interface; the pin is in input pull-up during reset and after internal reset release."+ },+ {+ "number": "27",+ "name": "PD2/TIM3_CH1",+ "type": "bidirectional",+ "description": "Port D2 high sink I/O that serves as TIM3 channel 1; option AFR1 remaps it to TIM2_CH3."+ },+ {+ "number": "28",+ "name": "PD3/TIM2_CH2",+ "type": "bidirectional",+ "description": "Port D3 high sink I/O that serves as TIM2 channel 2; option AFR0 remaps it to the ADC_ETR input."+ },+ {+ "number": "29",+ "name": "PD4/TIM2_CH1",+ "type": "bidirectional",+ "description": "Port D4 high sink I/O that serves as TIM2 channel 1; option AFR7 makes it the BEEP output."+ },+ {+ "number": "30",+ "name": "PD5/UART2_TX",+ "type": "bidirectional",+ "description": "Port D5 I/O that serves as the UART2 data transmit output UART2_TX."+ },+ {+ "number": "31",+ "name": "PD6/UART2_RX",+ "type": "bidirectional",+ "description": "Port D6 I/O that serves as the UART2 data receive input UART2_RX."+ },+ {+ "number": "32",+ "name": "PD7/TLI",+ "type": "bidirectional",+ "description": "Port D7 I/O that serves as the top level interrupt input TLI; option AFR4 remaps it to TIM1_CH4."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The LQFP32 pin numbers were taken from the LQFP32/UFQFPN32 column of Table 5 (pages 26-29), which is; Pin 5 VCAP is listed as type S (power supply) in the datasheet. It is typed here as passive because ; NRST (pin 1) is listed as I/O in the datasheet pin table, so it is typed bidirectional. Many KiCad s"+ ],+ "pages_sent": 55,+ "cost_usd": 0.2159,+ "at": "2026-10-08T04:50:19"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588924061560397824",+ "pages": 121,+ "sha256": "b1007bc27bb78327",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 32,+ "described": 32,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "stm8s105k4t3c.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "be0e412f1c66fee70039b0e109e0cc7c823161dda97593718afa97569bc61ce3",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "stm8s105k4t3c-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "4221dd9a98dc4b22ae0ac195551914ce7de425142c100d81777c84418cdcae86",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}