component
STM32H750ZBT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.1
5 files changed
+676−413
README.md+125−89@@ -8,114 +8,150 @@ STM32H750ZBT6 from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin desc | Pin | Name | Type | Function | |---|---|---|---|-| 1 | PE2 | output | GPIO port E pin 2 with alternate functions including trace clock, SAI1 clock/data, SPI4 clock, and FMC address line 23. |-| 2 | PE3 | output | GPIO port E pin 3 with alternate functions including trace data 0, timer brake input, SAI1/SAI4 data, and FMC address line 19. |-| 3 | PE4 | output | GPIO port E pin 4 with alternate functions including trace data 1, SAI1 data, timer channel, SPI4 chip select, and FMC address line 20. |-| 4 | PE5 | output | GPIO port E pin 5 with alternate functions including trace data 2, SAI1 clock/data, SPI4 MISO, and FMC address line 21. |-| 5 | PE6 | output | GPIO port E pin 6 with alternate functions including trace data 3, timer brake input, SAI1 data, SPI4 MOSI, and FMC address line 22. |+| 1 | PE2 | bidirectional | GPIO port E pin 2 with alternate functions including trace clock, SAI1 clock/data, SPI4 clock, and FMC address line 23. |+| 2 | PE3 | bidirectional | GPIO port E pin 3 with alternate functions including trace data 0, timer brake input, SAI1/SAI4 data, and FMC address line 19. |+| 3 | PE4 | bidirectional | GPIO port E pin 4 with alternate functions including trace data 1, SAI1 data, timer channel, SPI4 chip select, and FMC address line 20. |+| 4 | PE5 | bidirectional | GPIO port E pin 5 with alternate functions including trace data 2, SAI1 clock/data, SPI4 MISO, and FMC address line 21. |+| 5 | PE6 | bidirectional | GPIO port E pin 6 with alternate functions including trace data 3, timer brake input, SAI1 data, SPI4 MOSI, and FMC address line 22. | | 6 | VBAT | power_in | Backup battery supply voltage input (1.2 to 3.6 V) for backup domain when main supply is off. |-| 7 | PC13 | output | GPIO port C pin 13 with EVENTOUT alternate function and RTC tamper/wakeup capability. |-| 8 | PC14-OSC32_IN | output | GPIO port C pin 14 / 32 kHz oscillator input for LSE clock source. |-| 9 | PC15-OSC32_OUT | output | GPIO port C pin 15 / 32 kHz oscillator output for LSE clock source. |-| 10 | PF0 | output | GPIO port F pin 0 with alternate functions including I2C2 data and FMC address line 0. |-| 11 | PF1 | output | GPIO port F pin 1 with alternate functions including I2C2 clock and FMC address line 1. |-| 12 | PF2 | output | GPIO port F pin 2 with alternate functions including I2C2 SMBus alert and FMC address line 2. |-| 13 | PF3 | output | GPIO port F pin 3 with alternate functions for FMC address line 3 and ADC3 analog input. |-| 14 | PF4 | output | GPIO port F pin 4 with alternate functions for FMC address line 4 and ADC3 analog input channels. |-| 15 | PF5 | output | GPIO port F pin 5 with alternate functions for FMC address line 5 and ADC3 analog input. |+| 7 | PC13 | bidirectional | GPIO port C pin 13 with EVENTOUT alternate function and RTC tamper/wakeup capability. |+| 8 | PC14-OSC32_IN (OSC32_IN) | bidirectional | GPIO port C pin 14 / 32 kHz oscillator input for LSE clock source. |+| 9 | PC15-OSC32_OUT (OSC32_OUT) | bidirectional | GPIO port C pin 15 / 32 kHz oscillator output for LSE clock source. |+| 10 | PF0 | bidirectional | GPIO port F pin 0 with alternate functions including I2C2 data and FMC address line 0. |+| 11 | PF1 | bidirectional | GPIO port F pin 1 with alternate functions including I2C2 clock and FMC address line 1. |+| 12 | PF2 | bidirectional | GPIO port F pin 2 with alternate functions including I2C2 SMBus alert and FMC address line 2. |+| 13 | PF3 | bidirectional | GPIO port F pin 3 with alternate functions for FMC address line 3 and ADC3 analog input. |+| 14 | PF4 | bidirectional | GPIO port F pin 4 with alternate functions for FMC address line 4 and ADC3 analog input channels. |+| 15 | PF5 | bidirectional | GPIO port F pin 5 with alternate functions for FMC address line 5 and ADC3 analog input. | | 16 | VSS | power_in | Ground reference pin for digital logic and I/O circuits. | | 17 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. |-| 18 | PF6 | output | GPIO port F pin 6 with alternate functions including timer channel, SPI5 chip select, SAI1/SAI4 data, UART7 RX, and QUADSPI bank 1 I/O. |-| 19 | PF7 | output | GPIO port F pin 7 with alternate functions including timer channel, SPI5 clock, SAI1 MCLK, UART7 TX, and QUADSPI bank 1 I/O. |-| 20 | PF8 | output | GPIO port F pin 8 with alternate functions including timer channels, SPI5 MISO, SAI1 clock, UART7 flow control, and QUADSPI bank 1 I/O. |-| 21 | PF9 | output | GPIO port F pin 9 with alternate functions including timer channel, SPI5 MOSI, SAI1 frame sync, UART7 CTS, and QUADSPI bank 1 I/O. |-| 22 | PF10 | output | GPIO port F pin 10 with alternate functions including timer brake input, SAI1 data, QUADSPI clock, and FMC display enable output. |-| 23 | PH0-OSC_IN | output | GPIO port H pin 0 / main oscillator input pin for HSE crystal or external clock. |-| 24 | PH1-OSC_OUT | output | GPIO port H pin 1 / main oscillator output pin for HSE crystal oscillator. |-| 25 | NRST | bidirectional | Reset pin with embedded weak pull-up resistor; active low input for device reset. |-| 26 | PC0 | output | GPIO port C pin 0 with alternate functions including DFSDM clock/data, SAI2 frame sync, OTG HS USB, FMC SDRAM write enable, and ADC123 analog input. |-| 27 | PC1 | output | GPIO port C pin 1 with alternate functions including trace data 0, SAI1 data, SPI2/I2S2 MOSI, SDMMC2 clock, Ethernet MDC, and ADC123 analog input. |-| 28 | PC2_C | passive | Analog-only GPIO port C pin 2 (alternative pad with analog switch) for DFSDM, SPI2/I2S2, OTG HS USB, Ethernet, FMC, and ADC3 analog input. |-| 29 | PC3_C | passive | Analog-only GPIO port C pin 3 (alternative pad with analog switch) for DFSDM, SPI2/I2S2, OTG HS USB, Ethernet, FMC, and ADC12 analog input. |+| 18 | PF6 | bidirectional | GPIO port F pin 6 with alternate functions including timer channel, SPI5 chip select, SAI1/SAI4 data, UART7 RX, and QUADSPI bank 1 I/O. |+| 19 | PF7 | bidirectional | GPIO port F pin 7 with alternate functions including timer channel, SPI5 clock, SAI1 MCLK, UART7 TX, and QUADSPI bank 1 I/O. |+| 20 | PF8 | bidirectional | GPIO port F pin 8 with alternate functions including timer channels, SPI5 MISO, SAI1 clock, UART7 flow control, and QUADSPI bank 1 I/O. |+| 21 | PF9 | bidirectional | GPIO port F pin 9 with alternate functions including timer channel, SPI5 MOSI, SAI1 frame sync, UART7 CTS, and QUADSPI bank 1 I/O. |+| 22 | PF10 | bidirectional | GPIO port F pin 10 with alternate functions including timer brake input, SAI1 data, QUADSPI clock, and FMC display enable output. |+| 23 | PH0-OSC_IN (PH0) | bidirectional | GPIO port H pin 0 / main oscillator input pin for HSE crystal or external clock. |+| 24 | PH1-OSC_OUT (PH1) | bidirectional | GPIO port H pin 1 / main oscillator output pin for HSE crystal oscillator. |+| 25 | NRST | input | Reset pin with embedded weak pull-up resistor; active low input for device reset. |+| 26 | PC0 | bidirectional | GPIO port C pin 0 with alternate functions including DFSDM clock/data, SAI2 frame sync, OTG HS USB, FMC SDRAM write enable, and ADC123 analog input. |+| 27 | PC1 | bidirectional | GPIO port C pin 1 with alternate functions including trace data 0, SAI1 data, SPI2/I2S2 MOSI, SDMMC2 clock, Ethernet MDC, and ADC123 analog input. |+| 28 | PC2_C | bidirectional | Analog-only GPIO port C pin 2 (alternative pad with analog switch) for DFSDM, SPI2/I2S2, OTG HS USB, Ethernet, FMC, and ADC3 analog input. |+| 29 | PC3_C | bidirectional | Analog-only GPIO port C pin 3 (alternative pad with analog switch) for DFSDM, SPI2/I2S2, OTG HS USB, Ethernet, FMC, and ADC12 analog input. | | 30 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. | | 31 | VSSA | power_in | Analog ground reference pin for ADC, DAC, comparator, and operational amplifier circuits. | | 32 | VREF+ | power_in | Positive analog reference voltage input pin (1.62 to 3.6 V) for ADC/DAC peripheral circuitry. | | 33 | VDDA | power_in | Analog positive supply voltage (1.62 to 3.6 V) for ADC, DAC, comparator, operational amplifier, and VREFBUF. |-| 34 | PA0 | output | GPIO port A pin 0 with alternate functions including timer channels, USART2 CTS, UART4 TX, SDMMC2 command, and ADC1 analog input with wakeup capability. |-| 35 | PA1 | output | GPIO port A pin 1 with alternate functions including timer channels, LPUART/LPTIM output, USART2 RTS, UART4 RX, QUADSPI I/O, Ethernet clock, and ADC1 analog input. |-| 36 | PA2 | output | GPIO port A pin 2 with alternate functions including timer channels, LPTIM output, USART2 TX, Ethernet MDIO, and ADC12 analog input with wakeup capability. |-| 37 | PA3 | output | GPIO port A pin 3 with alternate functions including timer channels, LPTIM output, USART2 RX, LCD data, OTG HS USB, and ADC12 analog input. |+| 34 | PA0 | bidirectional | GPIO port A pin 0 with alternate functions including timer channels, USART2 CTS, UART4 TX, SDMMC2 command, and ADC1 analog input with wakeup capability. |+| 35 | PA1 | bidirectional | GPIO port A pin 1 with alternate functions including timer channels, LPUART/LPTIM output, USART2 RTS, UART4 RX, QUADSPI I/O, Ethernet clock, and ADC1 analog input. |+| 36 | PA2 | bidirectional | GPIO port A pin 2 with alternate functions including timer channels, LPTIM output, USART2 TX, Ethernet MDIO, and ADC12 analog input with wakeup capability. |+| 37 | PA3 | bidirectional | GPIO port A pin 3 with alternate functions including timer channels, LPTIM output, USART2 RX, LCD data, OTG HS USB, and ADC12 analog input. | | 38 | VSS | power_in | Ground reference pin for digital logic and I/O circuits. | | 39 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. |-| 40 | PA4 | output | GPIO port A pin 4 (3.3 V tolerant) with alternate functions including timer ETR, SPI chip selects, USART2 CK, OTG HS SOF, DCMI HSYNC, LCD VSYNC, and DAC1 analog output. |-| 41 | PA5 | output | GPIO port A pin 5 (3.3 V tolerant) with alternate functions including timer channel, SPI1/SPI6 clock, OTG HS clock, LCD data, and DAC1 analog output. |-| 42 | PA6 | output | GPIO port A pin 6 with alternate functions including timer brake/channels, SPI1 MISO, timer output compare, Ethernet RX, DCMI pixel clock, and ADC12 analog input. |-| 43 | PA7 | output | GPIO port A pin 7 (3.3 V tolerant) with alternate functions including timer channel, SPI1 MOSI, Ethernet RX, FMC SDRAM control, OPAMP1 input, and ADC12 analog input. |-| 44 | PC4 | output | GPIO port C pin 4 (3.3 V tolerant) with alternate functions including DFSDM clock, I2S1 MCK, SPDIFRX input, Ethernet RX, and FMC SDRAM control. |-| 45 | PC5 | output | GPIO port C pin 5 (3.3 V tolerant) with alternate functions including SAI1 data, DFSDM data, SPDIFRX input, Ethernet RX, FMC SDRAM control, COMP output, and ADC12 analog input. |-| 46 | PB0 | output | GPIO port B pin 0 with alternate functions including timer channels, DFSDM output, UART4 CTS, LCD data, OTG HS USB, Ethernet RX, OPAMP1 input, and ADC12 analog input. |-| 47 | PB1 | output | GPIO port B pin 1 (3.3 V tolerant, USB option) with alternate functions including timer channel, DFSDM data, LCD data, OTG HS USB, Ethernet RX, and COMP1 input. |-| 48 | PB2 | output | GPIO port B pin 2 with alternate functions including RTC output, SAI1 data, DFSDM clock, SPI3 MOSI, QUADSPI clock, and COMP1 input. |-| 49 | PF11 | output | GPIO port F pin 11 with alternate functions including SPI5 MOSI, SAI2 data, FMC SDRAM address, DCMI data, and ADC1 analog input. |-| 50 | PF12 | output | GPIO port F pin 12 with alternate functions for FMC address line 6 and ADC1 analog input. |+| 40 | PA4 | bidirectional | GPIO port A pin 4 (3.3 V tolerant) with alternate functions including timer ETR, SPI chip selects, USART2 CK, OTG HS SOF, DCMI HSYNC, LCD VSYNC, and DAC1 analog output. |+| 41 | PA5 | bidirectional | GPIO port A pin 5 (3.3 V tolerant) with alternate functions including timer channel, SPI1/SPI6 clock, OTG HS clock, LCD data, and DAC1 analog output. |+| 42 | PA6 | bidirectional | GPIO port A pin 6 with alternate functions including timer brake/channels, SPI1 MISO, timer output compare, Ethernet RX, DCMI pixel clock, and ADC12 analog input. |+| 43 | PA7 | bidirectional | GPIO port A pin 7 (3.3 V tolerant) with alternate functions including timer channel, SPI1 MOSI, Ethernet RX, FMC SDRAM control, OPAMP1 input, and ADC12 analog input. |+| 44 | PC4 | bidirectional | GPIO port C pin 4 (3.3 V tolerant) with alternate functions including DFSDM clock, I2S1 MCK, SPDIFRX input, Ethernet RX, and FMC SDRAM control. |+| 45 | PC5 | bidirectional | GPIO port C pin 5 (3.3 V tolerant) with alternate functions including SAI1 data, DFSDM data, SPDIFRX input, Ethernet RX, FMC SDRAM control, COMP output, and ADC12 analog input. |+| 46 | PB0 | bidirectional | GPIO port B pin 0 with alternate functions including timer channels, DFSDM output, UART4 CTS, LCD data, OTG HS USB, Ethernet RX, OPAMP1 input, and ADC12 analog input. |+| 47 | PB1 | bidirectional | GPIO port B pin 1 (3.3 V tolerant, USB option) with alternate functions including timer channel, DFSDM data, LCD data, OTG HS USB, Ethernet RX, and COMP1 input. |+| 48 | PB2 | bidirectional | GPIO port B pin 2 with alternate functions including RTC output, SAI1 data, DFSDM clock, SPI3 MOSI, QUADSPI clock, and COMP1 input. |+| 49 | PF11 | bidirectional | GPIO port F pin 11 with alternate functions including SPI5 MOSI, SAI2 data, FMC SDRAM address, DCMI data, and ADC1 analog input. |+| 50 | PF12 | bidirectional | GPIO port F pin 12 with alternate functions for FMC address line 6 and ADC1 analog input. | | 51 | VSS | power_in | Ground reference pin for digital logic and I/O circuits. | | 52 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. |-| 53 | PF13 | output | GPIO port F pin 13 with alternate functions including DFSDM data, I2C4 SMBus, FMC address line 7, and ADC2 analog input. |-| 54 | PF14 | output | GPIO port F pin 14 with alternate functions including DFSDM clock, I2C4 clock, FMC address line 8, and ADC2 analog input. |-| 55 | PF15 | output | GPIO port F pin 15 with alternate functions including I2C4 data and FMC address line 9. |-| 56 | PG0 | output | GPIO port G pin 0 with alternate function for FMC address line 10. |-| 57 | PG1 | output | GPIO port G pin 1 (3.3 V tolerant) with alternate functions for FMC address line 11 and OPAMP2 input. |-| 58 | PE7 | output | GPIO port E pin 7 (3.3 V tolerant) with alternate functions including timer ETR, DFSDM data, UART7 RX, QUADSPI I/O, FMC data, OPAMP2 output, and COMP2 input. |-| 59 | PE8 | output | GPIO port E pin 8 (3.3 V tolerant) with alternate functions including timer channel, DFSDM clock, UART7 TX, QUADSPI I/O, FMC data, and COMP2 input. |-| 60 | PE9 | output | GPIO port E pin 9 (3.3 V tolerant) with alternate functions including timer channel, DFSDM output, UART7 flow control, QUADSPI I/O, FMC data, and COMP2 input. |+| 53 | PF13 | bidirectional | GPIO port F pin 13 with alternate functions including DFSDM data, I2C4 SMBus, FMC address line 7, and ADC2 analog input. |+| 54 | PF14 | bidirectional | GPIO port F pin 14 with alternate functions including DFSDM clock, I2C4 clock, FMC address line 8, and ADC2 analog input. |+| 55 | PF15 | bidirectional | GPIO port F pin 15 with alternate functions including I2C4 data and FMC address line 9. |+| 56 | PG0 | bidirectional | GPIO port G pin 0 with alternate function for FMC address line 10. |+| 57 | PG1 | bidirectional | GPIO port G pin 1 (3.3 V tolerant) with alternate functions for FMC address line 11 and OPAMP2 input. |+| 58 | PE7 | bidirectional | GPIO port E pin 7 (3.3 V tolerant) with alternate functions including timer ETR, DFSDM data, UART7 RX, QUADSPI I/O, FMC data, OPAMP2 output, and COMP2 input. |+| 59 | PE8 | bidirectional | GPIO port E pin 8 (3.3 V tolerant) with alternate functions including timer channel, DFSDM clock, UART7 TX, QUADSPI I/O, FMC data, and COMP2 input. |+| 60 | PE9 | bidirectional | GPIO port E pin 9 (3.3 V tolerant) with alternate functions including timer channel, DFSDM output, UART7 flow control, QUADSPI I/O, FMC data, and COMP2 input. | | 61 | VSS | power_in | Ground reference pin for digital logic and I/O circuits. | | 62 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. |-| 63 | PE10 | output | GPIO port E pin 10 with alternate functions including timer channel, DFSDM data, UART7 CTS, QUADSPI I/O, FMC data, LCD data, and COMP2 input. |-| 64 | PE11 | output | GPIO port E pin 11 with alternate functions including timer channel, SPI4 chip select, SAI2 data, FMC data, and LCD data. |-| 65 | PE12 | output | GPIO port E pin 12 with alternate functions including timer channel, DFSDM data, SPI4 clock, SAI2 clock, FMC data, COMP1 output, and LCD data. |-| 66 | PE13 | output | GPIO port E pin 13 with alternate functions including timer channel, DFSDM clock, SPI4 MISO, SAI2 frame sync, FMC data, COMP2 output, and LCD display enable. |-| 67 | VSS | power_in | Ground reference pin for digital logic and I/O circuits. |-| 68 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. |-| 69 | PE14 | output | GPIO port E pin 14 with alternate functions including timer channel, SPI4 MOSI, SAI2 MCLK, FMC data, and LCD clock. |-| 70 | PE15 | output | GPIO port E pin 15 with alternate functions including timer brake input, FMC data, COMP timer brake, and LCD data. |-| 71 | PB10 | output | GPIO port B pin 10 with alternate functions including timer channel, I2C2 clock, SPI2/I2S2 clock, DFSDM data, USART3 TX, QUADSPI chip select, OTG HS USB, Ethernet RX, and LCD data. |-| 72 | PB11 | output | GPIO port B pin 11 with alternate functions including timer channel, I2C2 data, DFSDM clock, USART3 RX, OTG HS USB, Ethernet TX, and LCD data. |-| 73 | PB12 | output | GPIO port B pin 12 (USB option) with alternate functions including timer brake, I2C2 SMBus, SPI2/I2S2 chip select, DFSDM data, USART3 CK, FDCAN2 RX, OTG HS USB, Ethernet TX, and UART5 RX. |-| 74 | PB13 | output | GPIO port B pin 13 (USB option) with alternate functions including timer channel, LPTIM output, SPI2/I2S2 clock, DFSDM clock, USART3 CTS, FDCAN2 TX, OTG HS USB, Ethernet TX, and UART5 TX with VBUS monitoring. |-| 75 | PB14 | output | GPIO port B pin 14 (USB option) with alternate functions including timer channels, USART1 TX, SPI2/I2S2 MISO, DFSDM data, USART3 RTS, UART4 RTS, SDMMC2 data, and OTG HS DM. |-| 76 | PB15 | output | GPIO port B pin 15 (USB option) with alternate functions including RTC reference input, timer channels, USART1 RX, SPI2/I2S2 MOSI, DFSDM clock, UART4 CTS, SDMMC2 data, and OTG HS DP. |-| 77 | PD8 | output | GPIO port D pin 8 with alternate functions including DFSDM clock, SAI3 clock, USART3 TX, SPDIFRX input, and FMC data. |-| 78 | PD9 | output | GPIO port D pin 9 with alternate functions including DFSDM data, SAI3 data, USART3 RX, FDCAN2 mode select, and FMC data. |-| 79 | PD10 | output | GPIO port D pin 10 with alternate functions including DFSDM output, SAI3 frame sync, USART3 CK, FDCAN2 mode select, FMC data, and LCD data. |-| 80 | PD11 | output | GPIO port D pin 11 with alternate functions including LPTIM2 input, I2C4 SMBus, USART3 CTS, QUADSPI I/O, and SAI2 data. |-| 81 | PD12 | output | GPIO port D pin 12 with alternate functions including LPTIM1 input, timer channel, LPTIM2 input, I2C4 clock, USART3 RTS, QUADSPI I/O, and SAI2 frame sync. |-| 82 | PD13 | output | GPIO port D pin 13 with alternate functions including LPTIM1 output, timer channel, I2C4 data, QUADSPI I/O, and SAI2 clock. |+| 63 | PE10 | bidirectional | GPIO port E pin 10 with alternate functions including timer channel, DFSDM data, UART7 CTS, QUADSPI I/O, FMC data, LCD data, and COMP2 input. |+| 64 | PE11 | bidirectional | GPIO port E pin 11 with alternate functions including timer channel, SPI4 chip select, SAI2 data, FMC data, and LCD data. |+| 65 | PE12 | bidirectional | GPIO port E pin 12 with alternate functions including timer channel, DFSDM data, SPI4 clock, SAI2 clock, FMC data, COMP1 output, and LCD data. |+| 66 | PE13 | bidirectional | GPIO port E pin 13 with alternate functions including timer channel, DFSDM clock, SPI4 MISO, SAI2 frame sync, FMC data, COMP2 output, and LCD display enable. |+| 67 | PE14 | bidirectional | GPIO port E pin 14 with alternate functions including timer channel, SPI4 MOSI, SAI2 MCLK, FMC data, and LCD clock. |+| 68 | PE15 | bidirectional | GPIO port E pin 15 with alternate functions including timer brake input, FMC data, COMP timer brake, and LCD data. |+| 69 | PB10 | bidirectional | GPIO port B pin 10 with alternate functions including timer channel, I2C2 clock, SPI2/I2S2 clock, DFSDM data, USART3 TX, QUADSPI chip select, OTG HS USB, Ethernet RX, and LCD data. |+| 70 | PB11 | bidirectional | GPIO port B pin 11 with alternate functions including timer channel, I2C2 data, DFSDM clock, USART3 RX, OTG HS USB, Ethernet TX, and LCD data. |+| 71 | VCAP | power_in | Regulator stabilization capacitor pin; connect 2.2 µF external capacitor with < 100 mΩ ESR for voltage regulation. |+| 72 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. |+| 73 | PB12 | bidirectional | GPIO port B pin 12 (USB option) with alternate functions including timer brake, I2C2 SMBus, SPI2/I2S2 chip select, DFSDM data, USART3 CK, FDCAN2 RX, OTG HS USB, Ethernet TX, and UART5 RX. |+| 74 | PB13 | bidirectional | GPIO port B pin 13 (USB option) with alternate functions including timer channel, LPTIM output, SPI2/I2S2 clock, DFSDM clock, USART3 CTS, FDCAN2 TX, OTG HS USB, Ethernet TX, and UART5 TX with VBUS monitoring. |+| 75 | PB14 | bidirectional | GPIO port B pin 14 (USB option) with alternate functions including timer channels, USART1 TX, SPI2/I2S2 MISO, DFSDM data, USART3 RTS, UART4 RTS, SDMMC2 data, and OTG HS DM. |+| 76 | PB15 | bidirectional | GPIO port B pin 15 (USB option) with alternate functions including RTC reference input, timer channels, USART1 RX, SPI2/I2S2 MOSI, DFSDM clock, UART4 CTS, SDMMC2 data, and OTG HS DP. |+| 77 | PD8 | bidirectional | GPIO port D pin 8 with alternate functions including DFSDM clock, SAI3 clock, USART3 TX, SPDIFRX input, and FMC data. |+| 78 | PD9 | bidirectional | GPIO port D pin 9 with alternate functions including DFSDM data, SAI3 data, USART3 RX, FDCAN2 mode select, and FMC data. |+| 79 | PD10 | bidirectional | GPIO port D pin 10 with alternate functions including DFSDM output, SAI3 frame sync, USART3 CK, FDCAN2 mode select, FMC data, and LCD data. |+| 80 | PD11 | bidirectional | GPIO port D pin 11 with alternate functions including LPTIM2 input, I2C4 SMBus, USART3 CTS, QUADSPI I/O, and SAI2 data. |+| 81 | PD12 | bidirectional | GPIO port D pin 12 with alternate functions including LPTIM1 input, timer channel, LPTIM2 input, I2C4 clock, USART3 RTS, QUADSPI I/O, and SAI2 frame sync. |+| 82 | PD13 | bidirectional | GPIO port D pin 13 with alternate functions including LPTIM1 output, timer channel, I2C4 data, QUADSPI I/O, and SAI2 clock. | | 83 | VSS | power_in | Ground reference pin for digital logic and I/O circuits. | | 84 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. |-| 85 | PD14 | output | GPIO port D pin 14 with alternate functions including timer channel, SAI3 MCLK, UART8 CTS, and FMC data. |-| 86 | PD15 | output | GPIO port D pin 15 with alternate functions including timer channel, SAI3 MCLK, UART8 RTS, and FMC data. |-| 87 | PG2 | output | GPIO port G pin 2 with alternate functions including timer brake input, FMC address line 12. |-| 88 | PG3 | output | GPIO port G pin 3 with alternate functions including timer brake input (2nd source), FMC address line 13. |-| 89 | PG4 | output | GPIO port G pin 4 with alternate functions including timer brake input (2nd source), FMC address BA0/line 14. |-| 90 | PG5 | output | GPIO port G pin 5 with alternate functions including timer ETR and FMC address BA1/line 15. |-| 91 | PG6 | output | GPIO port G pin 6 with alternate functions including timer brake input, high-resolution timer channel, QUADSPI chip select, FMC chip enable, DCMI data, and LCD data. |-| 92 | PG7 | output | GPIO port G pin 7 with alternate functions including high-resolution timer channel, SAI1 MCLK, USART6 CK, FMC interrupt, DCMI data, and LCD clock. |-| 93 | PG8 | output | GPIO port G pin 8 with alternate functions including timer ETR, SPI6 chip select, USART6 RTS, SPDIFRX input, Ethernet PPS, FMC SDRAM clock, and LCD data. |+| 85 | PD14 | bidirectional | GPIO port D pin 14 with alternate functions including timer channel, SAI3 MCLK, UART8 CTS, and FMC data. |+| 86 | PD15 | bidirectional | GPIO port D pin 15 with alternate functions including timer channel, SAI3 MCLK, UART8 RTS, and FMC data. |+| 87 | PG2 | bidirectional | GPIO port G pin 2 with alternate functions including timer brake input, FMC address line 12. |+| 88 | PG3 | bidirectional | GPIO port G pin 3 with alternate functions including timer brake input (2nd source), FMC address line 13. |+| 89 | PG4 | bidirectional | GPIO port G pin 4 with alternate functions including timer brake input (2nd source), FMC address BA0/line 14. |+| 90 | PG5 | bidirectional | GPIO port G pin 5 with alternate functions including timer ETR and FMC address BA1/line 15. |+| 91 | PG6 | bidirectional | GPIO port G pin 6 with alternate functions including timer brake input, high-resolution timer channel, QUADSPI chip select, FMC chip enable, DCMI data, and LCD data. |+| 92 | PG7 | bidirectional | GPIO port G pin 7 with alternate functions including high-resolution timer channel, SAI1 MCLK, USART6 CK, FMC interrupt, DCMI data, and LCD clock. |+| 93 | PG8 | bidirectional | GPIO port G pin 8 with alternate functions including timer ETR, SPI6 chip select, USART6 RTS, SPDIFRX input, Ethernet PPS, FMC SDRAM clock, and LCD data. | | 94 | VSS | power_in | Ground reference pin for digital logic and I/O circuits. |-| 95 | VDD33USB | power_in | USB domain positive supply voltage (3.0 to 3.6 V when USB used; 0 to 3.6 V when USB not used). |-| 96 | PC6 | output | GPIO port C pin 6 with alternate functions including high-resolution timer channel, timer channel, DFSDM clock, I2S2 MCK, USART6 TX, SDMMC1 data direction, FMC wait, SDMMC2 data, DCMI data, and LCD HSYNC. |-| 97 | PC7 | output | GPIO port C pin 7 with alternate functions including high-resolution timer channel, timer channel, DFSDM data, I2S3 MCK, USART6 RX, SDMMC1 data direction, FMC chip enable, SDMMC2 data, SWPMI TX, DCMI data, and LCD data. |-| 98 | PC8 | output | GPIO port C pin 8 with alternate functions including trace data 1, high-resolution timer channel, timer channel, USART6 CK, UART5 RTS, FMC chip enable, SWPMI RX, SDMMC1 data, and DCMI data. |-| 99 | PC9 | output | GPIO port C pin 9 with alternate functions including MCO2 clock output, timer channel, I2C3 data, I2S clock input, UART5 CTS, QUADSPI I/O, LCD data, SWPMI suspend, SDMMC1 data, and DCMI data. |-| 100 | PA8 | output | GPIO port A pin 8 with alternate functions including MCO1 clock output, timer channel, I2C3 clock, USART1 CK, OTG FS SOF, UART7 RX, LCD data, and EVENTOUT. |-| 101 | PA9 | output | GPIO port A pin 9 (USB option) with alternate functions including timer channel, LPUART1 TX, I2C3 SMBus, SPI2/I2S2 clock, USART1 TX, FDCAN1 mode select, DCMI data, and LCD data with VBUS monitoring. |-| 102 | PA10 | output | GPIO port A pin 10 (USB option) with alternate functions including timer channel, LPUART1 RX, USART1 RX, FDCAN1 mode select, OTG FS ID, Ethernet MDIO, LCD data, and DCMI data. |-| 103 | PA11 | output | GPIO port A pin 11 (USB option) with alternate functions including timer channel, LPUART1 CTS, SPI2/I2S2 chip select, UART4 RX, USART1 CTS, FDCAN1 RX, and OTG FS DM. |-| 104 | PA12 | output | GPIO port A pin 12 (USB option) with alternate functions including timer ETR, LPUART1 RTS, SPI2/I2S2 clock, UART4 TX, USART1 RTS, SAI2 frame sync, FDCAN1 TX, and OTG FS DP. |-| 105 | PA13 | output | GPIO port A pin 13 (JTAG/SWDIO debug interface) with debug pin functions JTMS-SWDIO and EVENTOUT. |+| 95 | VDD33_USB | power_in | USB domain positive supply voltage (3.0 to 3.6 V when USB used; 0 to 3.6 V when USB not used). |+| 96 | PC6 | bidirectional | GPIO port C pin 6 with alternate functions including high-resolution timer channel, timer channel, DFSDM clock, I2S2 MCK, USART6 TX, SDMMC1 data direction, FMC wait, SDMMC2 data, DCMI data, and LCD HSYNC. |+| 97 | PC7 | bidirectional | GPIO port C pin 7 with alternate functions including high-resolution timer channel, timer channel, DFSDM data, I2S3 MCK, USART6 RX, SDMMC1 data direction, FMC chip enable, SDMMC2 data, SWPMI TX, DCMI data, and LCD data. |+| 98 | PC8 | bidirectional | GPIO port C pin 8 with alternate functions including trace data 1, high-resolution timer channel, timer channel, USART6 CK, UART5 RTS, FMC chip enable, SWPMI RX, SDMMC1 data, and DCMI data. |+| 99 | PC9 | bidirectional | GPIO port C pin 9 with alternate functions including MCO2 clock output, timer channel, I2C3 data, I2S clock input, UART5 CTS, QUADSPI I/O, LCD data, SWPMI suspend, SDMMC1 data, and DCMI data. |+| 100 | PA8 | bidirectional | GPIO port A pin 8 with alternate functions including MCO1 clock output, timer channel, I2C3 clock, USART1 CK, OTG FS SOF, UART7 RX, LCD data, and EVENTOUT. |+| 101 | PA9 | bidirectional | GPIO port A pin 9 (USB option) with alternate functions including timer channel, LPUART1 TX, I2C3 SMBus, SPI2/I2S2 clock, USART1 TX, FDCAN1 mode select, DCMI data, and LCD data with VBUS monitoring. |+| 102 | PA10 | bidirectional | GPIO port A pin 10 (USB option) with alternate functions including timer channel, LPUART1 RX, USART1 RX, FDCAN1 mode select, OTG FS ID, Ethernet MDIO, LCD data, and DCMI data. |+| 103 | PA11 | bidirectional | GPIO port A pin 11 (USB option) with alternate functions including timer channel, LPUART1 CTS, SPI2/I2S2 chip select, UART4 RX, USART1 CTS, FDCAN1 RX, and OTG FS DM. |+| 104 | PA12 | bidirectional | GPIO port A pin 12 (USB option) with alternate functions including timer ETR, LPUART1 RTS, SPI2/I2S2 clock, UART4 TX, USART1 RTS, SAI2 frame sync, FDCAN1 TX, and OTG FS DP. |+| 105 | PA13 (JTMS/SWDIO) | bidirectional | GPIO port A pin 13 (JTAG/SWDIO debug interface) with debug pin functions JTMS-SWDIO and EVENTOUT. | | 106 | VCAP | power_in | Regulator stabilization capacitor pin; connect 2.2 µF external capacitor with < 100 mΩ ESR for voltage regulation. | | 107 | VSS | power_in | Ground reference pin for digital logic and I/O circuits. | | 108 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. |+| 109 | PA14 (JTCK/SWCLK) | bidirectional | |+| 110 | PA15 (JTDI) | bidirectional | |+| 111 | PC10 | bidirectional | |+| 112 | PC11 | bidirectional | |+| 113 | PC12 | bidirectional | |+| 114 | PD0 | bidirectional | |+| 115 | PD1 | bidirectional | |+| 116 | PD2 | bidirectional | |+| 117 | PD3 | bidirectional | |+| 118 | PD4 | bidirectional | |+| 119 | PD5 | bidirectional | |+| 120 | VSS | power_in | Ground reference pin for digital logic and I/O circuits. |+| 121 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. |+| 122 | PD6 | bidirectional | |+| 123 | PD7 | bidirectional | |+| 124 | PG9 | bidirectional | |+| 125 | PG10 | bidirectional | |+| 126 | PG11 | bidirectional | |+| 127 | PG12 | bidirectional | |+| 128 | PG13 | bidirectional | |+| 129 | PG14 | bidirectional | |+| 130 | VSS | power_in | Ground reference pin for digital logic and I/O circuits. |+| 131 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. |+| 132 | PG15 | bidirectional | |+| 133 | PB3 (JTDO/TRACESWO) | bidirectional | |+| 134 | PB4 (NJTRST) | bidirectional | |+| 135 | PB5 | bidirectional | |+| 136 | PB6 | bidirectional | |+| 137 | PB7 | bidirectional | |+| 138 | BOOT0 | input | |+| 139 | PB8 | bidirectional | |+| 140 | PB9 | bidirectional | |+| 141 | PE0 | bidirectional | |+| 142 | PE1 | bidirectional | |+| 143 | PDR_ON | power_in | |+| 144 | VDD | power_in | Main positive supply voltage pin (1.62 to 3.6 V) for digital logic circuits. | ## Key specifications
package.json+2−2@@ -1,6 +1,6 @@ { "slug": "stm32h750zbt6",- "version": "0.1.0",+ "version": "0.1.1", "type": "component", "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.", "tags": [@@ -733,4 +733,4 @@ "footprint": "viewers/footprint.html" } }-}+}
page.json+4−4@@ -4,7 +4,7 @@ "slug": "stm32h750zbt6", "title": "STM32H750ZBT6", "brief": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.1.1", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -760,7 +760,7 @@ "viewers/symbol.html", "viewers/footprint.html" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",+ "org": "adom" }
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y="53.34" length="middle" direction="pwr" rot="R180"/>+ <pin name="PG14" x="17.78" y="50.8" length="middle" direction="io" rot="R180"/>+ <pin name="PG13" x="17.78" y="48.26" length="middle" direction="io" rot="R180"/>+ <pin name="PG12" x="17.78" y="45.72" length="middle" direction="io" rot="R180"/>+ <pin name="PG11" x="17.78" y="43.18" length="middle" direction="io" rot="R180"/>+ <pin name="PG10" x="17.78" y="40.64" length="middle" direction="io" rot="R180"/>+ <pin name="PG9" x="17.78" y="38.1" length="middle" direction="io" rot="R180"/>+ <pin name="PD7" x="17.78" y="35.56" length="middle" direction="io" rot="R180"/>+ <pin name="PD6" x="17.78" y="33.02" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@9" x="17.78" y="30.48" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@6" x="17.78" y="27.94" length="middle" direction="pwr" rot="R180"/>+ <pin name="PD5" x="17.78" y="25.4" length="middle" direction="io" rot="R180"/>+ <pin name="PD4" x="17.78" y="22.86" length="middle" direction="io" rot="R180"/>+ <pin name="PD3" x="17.78" y="20.32" length="middle" direction="io" rot="R180"/>+ <pin name="PD2" x="17.78" y="17.78" length="middle" direction="io" rot="R180"/>+ <pin name="PD1" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>+ <pin name="PD0" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>+ <pin name="PC12" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>+ <pin name="PC11" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>+ <pin name="PC10" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>+ <pin name="PA15_JTDI" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>+ <pin name="PA14_JTCK/SWCLK" x="17.78" y="0" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@10" x="17.78" y="-2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@7" x="17.78" y="-5.08" length="middle" direction="pwr" rot="R180"/>+ <pin name="VCAP@2" x="17.78" y="-7.62" length="middle" direction="pwr" rot="R180"/>+ <pin name="PA13_JTMS/SWDIO" x="17.78" y="-10.16" length="middle" direction="io" rot="R180"/>+ <pin name="PA12" x="17.78" y="-12.7" length="middle" direction="io" rot="R180"/>+ <pin name="PA11" x="17.78" y="-15.24" length="middle" direction="io" rot="R180"/>+ <pin name="PA10" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>+ <pin name="PA9" x="17.78" y="-20.32" length="middle" direction="io" rot="R180"/>+ <pin name="PA8" x="17.78" y="-22.86" length="middle" direction="io" rot="R180"/>+ <pin name="PC9" x="17.78" y="-25.4" length="middle" direction="io" rot="R180"/>+ <pin name="PC8" x="17.78" y="-27.94" length="middle" direction="io" rot="R180"/>+ <pin name="PC7" x="17.78" y="-30.48" length="middle" direction="io" rot="R180"/>+ <pin name="PC6" x="17.78" y="-33.02" length="middle" direction="io" rot="R180"/>+ <pin name="VDD33_USB" x="17.78" y="-35.56" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@8" x="17.78" y="-38.1" length="middle" direction="pwr" rot="R180"/>+ <pin name="PG8" x="17.78" y="-40.64" length="middle" direction="io" rot="R180"/>+ <pin name="PG7" x="17.78" y="-43.18" length="middle" direction="io" rot="R180"/>+ <pin name="PG6" x="17.78" y="-45.72" length="middle" direction="io" rot="R180"/>+ <pin name="PG5" x="17.78" y="-48.26" length="middle" direction="io" rot="R180"/>+ <pin name="PG4" x="17.78" y="-50.8" length="middle" direction="io" rot="R180"/>+ <pin name="PG3" x="17.78" y="-53.34" length="middle" direction="io" rot="R180"/>+ <pin name="PG2" x="17.78" y="-55.88" length="middle" direction="io" rot="R180"/>+ <pin name="PD15" x="17.78" y="-58.42" length="middle" direction="io" rot="R180"/>+ <pin name="PD14" x="17.78" y="-60.96" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@11" x="17.78" y="-63.5" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@9" x="17.78" y="-66.04" length="middle" direction="pwr" rot="R180"/>+ <pin name="PD13" x="17.78" y="-68.58" length="middle" direction="io" rot="R180"/>+ <pin name="PD12" x="17.78" y="-71.12" length="middle" direction="io" rot="R180"/>+ <pin name="PD11" x="17.78" y="-73.66" length="middle" direction="io" rot="R180"/>+ <pin name="PD10" x="17.78" y="-76.2" length="middle" direction="io" rot="R180"/>+ <pin name="PD9" x="17.78" y="-78.74" length="middle" direction="io" rot="R180"/>+ <pin name="PD8" x="17.78" y="-81.28" length="middle" direction="io" rot="R180"/>+ <pin name="PB15" x="17.78" y="-83.82" length="middle" direction="io" rot="R180"/>+ <pin name="PB14" x="17.78" y="-86.36" length="middle" direction="io" rot="R180"/>+ <pin name="PB13" x="17.78" y="-88.9" length="middle" direction="io" rot="R180"/>+ <pin name="PB12" x="17.78" y="-91.44" length="middle" direction="io" rot="R180"/> </symbol> </symbols> <devicesets> <deviceset name="STM32H750ZBT6" prefix="U">- <description></description>+ <description>STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout checked against ST's open pin data</description> <gates> <gate name="G$1" symbol="STM32H750ZBT6" x="0" y="0"/> </gates>@@ -356,8 +393,8 @@ <connect gate="G$1" pin="PE6" pad="5"/> <connect gate="G$1" pin="VBAT" pad="6"/> <connect gate="G$1" pin="PC13" pad="7"/>- <connect gate="G$1" pin="PC14-OSC32_IN" pad="8"/>- <connect gate="G$1" pin="PC15-OSC32_OUT" pad="9"/>+ <connect gate="G$1" pin="PC14-OSC32_IN_OSC32_IN" pad="8"/>+ <connect gate="G$1" pin="PC15-OSC32_OUT_OSC32_OUT" pad="9"/> <connect gate="G$1" pin="PF0" pad="10"/> <connect gate="G$1" pin="PF1" pad="11"/> <connect gate="G$1" pin="PF2" pad="12"/>@@ -371,8 +408,8 @@ <connect gate="G$1" pin="PF8" pad="20"/> <connect gate="G$1" pin="PF9" pad="21"/> <connect gate="G$1" pin="PF10" pad="22"/>- <connect gate="G$1" pin="PH0-OSC_IN" pad="23"/>- <connect gate="G$1" pin="PH1-OSC_OUT" pad="24"/>+ <connect gate="G$1" pin="PH0-OSC_IN_PH0" pad="23"/>+ <connect gate="G$1" pin="PH1-OSC_OUT_PH1" pad="24"/> <connect gate="G$1" pin="NRST" pad="25"/> <connect gate="G$1" pin="PC0" pad="26"/> <connect gate="G$1" pin="PC1" pad="27"/>@@ -403,10 +440,64 @@ <connect gate="G$1" pin="VDD@4" pad="52"/> <connect gate="G$1" pin="PF13" pad="53"/> <connect gate="G$1" pin="PF14" pad="54"/>- <connect gate="G$1" pin="VDD@5" pad="108"/>- <connect gate="G$1" pin="VSS@4" pad="107"/>- <connect gate="G$1" pin="VCAP" pad="106"/>- <connect gate="G$1" pin="PA13" pad="105"/>+ <connect gate="G$1" pin="PF15" pad="55"/>+ <connect gate="G$1" pin="PG0" pad="56"/>+ <connect gate="G$1" pin="PG1" pad="57"/>+ <connect gate="G$1" pin="PE7" pad="58"/>+ <connect gate="G$1" pin="PE8" pad="59"/>+ <connect gate="G$1" pin="PE9" pad="60"/>+ <connect gate="G$1" pin="VSS@4" pad="61"/>+ <connect gate="G$1" pin="VDD@5" pad="62"/>+ <connect gate="G$1" pin="PE10" pad="63"/>+ <connect gate="G$1" pin="PE11" pad="64"/>+ <connect gate="G$1" pin="PE12" pad="65"/>+ <connect gate="G$1" pin="PE13" pad="66"/>+ <connect gate="G$1" pin="PE14" pad="67"/>+ <connect gate="G$1" pin="PE15" pad="68"/>+ <connect gate="G$1" pin="PB10" pad="69"/>+ <connect gate="G$1" pin="PB11" pad="70"/>+ <connect gate="G$1" pin="VCAP" pad="71"/>+ <connect gate="G$1" pin="VDD@6" pad="72"/>+ <connect gate="G$1" pin="VDD@7" pad="144"/>+ <connect gate="G$1" pin="PDR_ON" pad="143"/>+ <connect gate="G$1" pin="PE1" pad="142"/>+ <connect gate="G$1" pin="PE0" pad="141"/>+ <connect gate="G$1" pin="PB9" pad="140"/>+ <connect gate="G$1" pin="PB8" pad="139"/>+ <connect gate="G$1" pin="BOOT0" pad="138"/>+ <connect gate="G$1" pin="PB7" pad="137"/>+ <connect gate="G$1" pin="PB6" pad="136"/>+ <connect gate="G$1" pin="PB5" pad="135"/>+ <connect gate="G$1" pin="PB4_NJTRST" pad="134"/>+ <connect gate="G$1" pin="PB3_JTDO/TRACESWO" pad="133"/>+ <connect gate="G$1" pin="PG15" pad="132"/>+ <connect gate="G$1" pin="VDD@8" pad="131"/>+ <connect gate="G$1" pin="VSS@5" pad="130"/>+ <connect gate="G$1" pin="PG14" pad="129"/>+ <connect gate="G$1" pin="PG13" pad="128"/>+ <connect gate="G$1" pin="PG12" pad="127"/>+ <connect gate="G$1" pin="PG11" pad="126"/>+ <connect gate="G$1" pin="PG10" pad="125"/>+ <connect gate="G$1" pin="PG9" pad="124"/>+ <connect gate="G$1" pin="PD7" pad="123"/>+ <connect gate="G$1" pin="PD6" pad="122"/>+ <connect gate="G$1" pin="VDD@9" pad="121"/>+ <connect gate="G$1" pin="VSS@6" pad="120"/>+ <connect gate="G$1" pin="PD5" pad="119"/>+ <connect gate="G$1" pin="PD4" pad="118"/>+ <connect gate="G$1" pin="PD3" pad="117"/>+ <connect gate="G$1" pin="PD2" pad="116"/>+ <connect gate="G$1" pin="PD1" pad="115"/>+ <connect gate="G$1" pin="PD0" pad="114"/>+ <connect gate="G$1" pin="PC12" pad="113"/>+ <connect gate="G$1" pin="PC11" pad="112"/>+ <connect gate="G$1" pin="PC10" pad="111"/>+ <connect gate="G$1" pin="PA15_JTDI" pad="110"/>+ <connect gate="G$1" pin="PA14_JTCK/SWCLK" pad="109"/>+ <connect gate="G$1" pin="VDD@10" pad="108"/>+ <connect gate="G$1" pin="VSS@7" pad="107"/>+ <connect gate="G$1" pin="VCAP@2" pad="106"/>+ <connect gate="G$1" pin="PA13_JTMS/SWDIO" pad="105"/> <connect gate="G$1" pin="PA12" pad="104"/> <connect gate="G$1" pin="PA11" pad="103"/> <connect gate="G$1" pin="PA10" pad="102"/>@@ -416,8 +507,8 @@ <connect gate="G$1" pin="PC8" pad="98"/> <connect gate="G$1" pin="PC7" pad="97"/> <connect gate="G$1" pin="PC6" pad="96"/>- <connect gate="G$1" pin="VDD33USB" pad="95"/>- <connect gate="G$1" pin="VSS@5" pad="94"/>+ <connect gate="G$1" pin="VDD33_USB" pad="95"/>+ <connect gate="G$1" pin="VSS@8" pad="94"/> <connect gate="G$1" pin="PG8" pad="93"/> <connect gate="G$1" pin="PG7" pad="92"/> <connect gate="G$1" pin="PG6" pad="91"/>@@ -427,8 +518,8 @@ <connect gate="G$1" pin="PG2" pad="87"/> <connect gate="G$1" pin="PD15" pad="86"/> <connect gate="G$1" pin="PD14" pad="85"/>- <connect gate="G$1" pin="VDD@6" pad="84"/>- <connect gate="G$1" pin="VSS@6" pad="83"/>+ <connect gate="G$1" pin="VDD@11" pad="84"/>+ <connect gate="G$1" pin="VSS@9" pad="83"/> <connect gate="G$1" pin="PD13" pad="82"/> <connect gate="G$1" pin="PD12" pad="81"/> <connect gate="G$1" pin="PD11" pad="80"/>@@ -439,26 +530,18 @@ <connect gate="G$1" pin="PB14" pad="75"/> <connect gate="G$1" pin="PB13" pad="74"/> <connect gate="G$1" pin="PB12" pad="73"/>- <connect gate="G$1" pin="PB11" pad="72"/>- <connect gate="G$1" pin="PB10" pad="71"/>- <connect gate="G$1" pin="PE15" pad="70"/>- <connect gate="G$1" pin="PE14" pad="69"/>- <connect gate="G$1" pin="VDD@7" pad="68"/>- <connect gate="G$1" pin="VSS@7" pad="67"/>- <connect gate="G$1" pin="PE13" pad="66"/>- <connect gate="G$1" pin="PE12" pad="65"/>- <connect gate="G$1" pin="PE11" pad="64"/>- <connect gate="G$1" pin="PE10" pad="63"/>- <connect gate="G$1" pin="VDD@8" pad="62"/>- <connect gate="G$1" pin="VSS@8" pad="61"/>- <connect gate="G$1" pin="PE9" pad="60"/>- <connect gate="G$1" pin="PE8" pad="59"/>- <connect gate="G$1" pin="PE7" pad="58"/>- <connect gate="G$1" pin="PG1" pad="57"/>- <connect gate="G$1" pin="PG0" pad="56"/>- <connect gate="G$1" pin="PF15" pad="55"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="STM32H750ZBT6" constant="no"/>+ <attribute name="MANUFACTURER" value="STMicroelectronics" constant="no"/>+ <attribute name="DATASHEET" value="https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588886273507803136" constant="no"/>+ <attribute name="ADOM_WIKI" value="https://wiki.adom.inc/adom/stm32h750zbt6" constant="no"/>+ <attribute name="MOUSER_PN" value="511-STM32H750ZBT6" constant="no"/>+ <attribute name="DIGIKEY_PN" value="497-STM32H750ZBT6-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C730202" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>