component
STM32G0B1CET6N
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
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README.mdadded+84@@ -0,0 +1,84 @@+# STM32G0B1CET6N++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)++STM32G0B1CET6N from STMicroelectronics, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PC13 | bidirectional | FT I/O supplied through the power switch (3 mA sink limit, output max 2 MHz with 30 pF load, not for driving LEDs); AF TIM1_BKIN, additional functions TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2. |+| 2 | PC14-OSC32_IN | bidirectional | FT I/O supplied through the power switch (limited output use); AF TIM1_BKIN2, additional function OSC32_IN for the 32.768 kHz crystal. |+| 3 | PC15-OSC32_OUT | bidirectional | FT I/O supplied through the power switch (limited output use); AF OSC32_EN, OSC_EN, TIM15_BKIN, additional function OSC32_OUT for the 32.768 kHz crystal. |+| 4 | VBAT | power_in | Backup supply (1.55 V to 3.6 V) for RTC, TAMP, LSE oscillator and backup registers when VDD is not present. |+| 5 | VREF+ | power_in | Analog reference voltage input or VREFBUF output (VREFBUF_OUT); must equal VDDA when VDDA < 2 V, otherwise between 2 V and VDDA. |+| 6 | VDD/VDDA | power_in | Main digital and analog supply, 1.7 V to 3.6 V, also supplies VDDIO1; decouple with 100 nF + 4.7 µF ceramic capacitors. |+| 7 | VSS/VSSA | power_in | Ground for digital and analog supplies. |+| 8 | PF0-OSC_IN | bidirectional | FT I/O with AF CRS1_SYNC, EVENTOUT, TIM14_CH1; additional function OSC_IN for the 4-48 MHz crystal oscillator. |+| 9 | PF1-OSC_OUT | bidirectional | FT I/O with AF OSC_EN, EVENTOUT, TIM15_CH1N; additional function OSC_OUT for the 4-48 MHz crystal oscillator. |+| 10 | PF2-NRST | bidirectional | Bidirectional reset pin with embedded weak pull-up; also GPIO with AF MCO, LPUART2_TX, LPUART2_RTS_DE. |+| 11 | PA0 | bidirectional | FT_a I/O with AF SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT; additional COMP1_INM8, ADC_IN0, TAMP_IN2, WKUP1. |+| 12 | PA1 | bidirectional | FT_ea I/O with AF SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT; additional COMP1_INP2, ADC_IN1. |+| 13 | PA2 | bidirectional | FT_a I/O with AF SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT; additional COMP2_INM8, ADC_IN2, WKUP4, LSCO. |+| 14 | PA3 | bidirectional | FT_ea I/O with AF SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT; additional COMP2_INP2, ADC_IN3. |+| 15 | PA4 | bidirectional | TT_a I/O (3.6 V tolerant) with AF SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USB_NOE, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS; additional ADC_IN4, DAC1_OUT1, RTC_OUT2. |+| 16 | PA5 | bidirectional | TT_ea I/O (3.6 V tolerant) with AF SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT; additional ADC_IN5, DAC1_OUT2. |+| 17 | PA6 | bidirectional | FT_ea I/O with AF SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA; additional ADC_IN6. |+| 18 | PA7 | bidirectional | FT_a I/O with AF SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL; additional ADC_IN7. |+| 19 | PB0 | bidirectional | FT_ea I/O with AF SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS; additional COMP3_INP0, ADC_IN8. |+| 20 | PB1 | bidirectional | FT_ea I/O with AF TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE; additional COMP1_INM6, ADC_IN9. |+| 21 | PB2 | bidirectional | FT_ea I/O with AF SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT; additional COMP1_INP1, COMP3_INM6, ADC_IN10. |+| 22 | PB10 | bidirectional | FT_fa I/O (Fm+ capable) with AF CEC, LPUART1_RX, TIM2_CH3, USART3_TX, SPI2_SCK/I2S2_CK, I2C2_SCL, COMP1_OUT; additional ADC_IN11. |+| 23 | PB11 | bidirectional | FT_fa I/O (Fm+ capable) with AF SPI2_MOSI/I2S2_SD, LPUART1_TX, TIM2_CH4, USART3_RX, I2C2_SDA, COMP2_OUT; additional ADC_IN15. |+| 24 | PB12 | bidirectional | FT_fa I/O (Fm+ capable) with AF SPI2_NSS/I2S2_WS, LPUART1_RTS_DE, TIM1_BKIN, FDCAN2_RX, TIM15_BKIN, UCPD2_FRSTX, EVENTOUT, I2C2_SMBA; additional ADC_IN16. |+| 25 | PB13 | bidirectional | FT_f I/O (Fm+ capable) with AF SPI2_SCK/I2S2_CK, LPUART1_CTS, TIM1_CH1N, FDCAN2_TX, USART3_CTS, TIM15_CH1N, I2C2_SCL, EVENTOUT. |+| 26 | PB14 | bidirectional | FT_f I/O (Fm+ capable) with AF SPI2_MISO/I2S2_MCK, UCPD1_FRSTX, TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1, I2C2_SDA, EVENTOUT, USART6_RTS_DE_CK. |+| 27 | PB15 | bidirectional | FT_fc I/O (Fm+, USB Type-C PD capable) with AF SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2, EVENTOUT, USART6_CTS; additional UCPD1_CC2, RTC_REFIN; may have a pull-down after reset. |+| 28 | PA8 | bidirectional | FT_fc I/O (Fm+, USB Type-C PD capable) with AF MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA; additional UCPD1_CC1; may have a pull-down after reset. |+| 29 | PA9 | bidirectional | FT_fd I/O (Fm+, UCPD dead battery) with AF MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL; additional UCPD1_DBCC1; can be remapped in place of PA11. |+| 30 | VSS | power_in | Ground pin on the N version, additional to VSS/VSSA. |+| 31 | VDDIO2 | power_in | Independent I/O supply of 1.6 V to 3.6 V for selected I/Os and VDDUSB; must not be applied without valid VDD. |+| 32 | PA10 | bidirectional | FT_fd I/O (Fm+, UCPD dead battery) with AF SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA; additional UCPD1_DBCC2; can be remapped in place of PA12. |+| 33 | PA11 [PA9] | bidirectional | FT_f I/O (Fm+) with AF SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT; additional USB_DM; PA9 can be remapped here via SYSCFG_CFGR1. |+| 34 | PA12 [PA10] | bidirectional | FT_f I/O (Fm+) with AF SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT; additional USB_DP; PA10 can be remapped here via SYSCFG_CFGR1. |+| 35 | PA13 | bidirectional | FT_e I/O configured as SWDIO at reset with internal pull-up active; AF IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX. |+| 36 | PA14-BOOT0 | bidirectional | FT I/O configured as SWCLK at reset with internal pull-down active; AF USART2_TX, EVENTOUT, LPUART2_TX; additional function BOOT0. |+| 37 | PA15 | bidirectional | FT I/O with AF SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS. |+| 38 | PD0 | bidirectional | FT_c I/O (USB Type-C PD capable) with AF EVENTOUT, SPI2_NSS/I2S2_WS, TIM16_CH1, FDCAN1_RX; additional UCPD2_CC1; may have a pull-down after reset. |+| 39 | PD1 | bidirectional | FT_d I/O (UCPD dead battery) with AF EVENTOUT, SPI2_SCK/I2S2_CK, TIM17_CH1, FDCAN1_TX; additional UCPD2_DBCC1; may have a pull-down after reset. |+| 40 | PD2 | bidirectional | FT_c I/O (USB Type-C PD capable) with AF USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N, USART5_RX; additional UCPD2_CC2; may have a pull-down after reset. |+| 41 | PD3 | bidirectional | FT_d I/O (UCPD dead battery) with AF USART2_CTS, SPI2_MISO/I2S2_MCK, TIM1_CH2N, USART5_TX; additional UCPD2_DBCC2; may have a pull-down after reset. |+| 42 | PB3 | bidirectional | FT_a I/O with AF SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK; additional COMP2_INM6. |+| 43 | PB4 | bidirectional | FT_a I/O with AF SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO; additional COMP2_INP0. |+| 44 | PB5 | bidirectional | FT I/O with AF SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI; additional WKUP6. |+| 45 | PB6 | bidirectional | FT_fa I/O (Fm+ capable) with AF USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX; additional COMP2_INP1. |+| 46 | PB7 | bidirectional | FT_fa I/O (Fm+ capable) with AF USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX; additional COMP2_INM7, PVD_IN. |+| 47 | PB8 | bidirectional | FT_f I/O (Fm+ capable) with AF CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3. |+| 48 | PB9 | bidirectional | FT_f I/O (Fm+ capable) with AF IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-48(7x7) |+| Category | Embedded Processors & Controllers |+| Pins | 48 |++## CAD (KiCad official)++- Symbol: `STM32G0B1CET6N`+- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`+- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)+- 3D model files: `stm32g0b1cet6n-etched.step` / `stm32g0b1cet6n-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32g0b1cet6n.step` / `stm32g0b1cet6n.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589836521785630720) (159 pp, sha256 `ee33614bd414ac41`, retrieved 2026-10-01, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stm32g0b1cet6n-datasheet.pdf)
page.jsonadded+397@@ -0,0 +1,397 @@+{+ "slug": "stm32g0b1cet6n",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "stm32g0b1cet6n",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "stm32g0b1cet6n.kicad_sym",+ "stm32g0b1cet6n.kicad_mod",+ "stm32g0b1cet6n.glb",+ "stm32g0b1cet6n.step",+ "stm32g0b1cet6n.lbr",+ "docs/hero.png",+ "docs/stm32g0b1cet6n-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "STM32G0B1CET6N",+ "manufacturer": "STMicroelectronics",+ "package": "LQFP-48(7x7)",+ "pin_count": 48,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589836521785630720",+ "parts": {+ "symbol": "stm32g0b1cet6n.kicad_sym",+ "footprint": "stm32g0b1cet6n.kicad_mod",+ "model_3d": "stm32g0b1cet6n-etched.glb",+ "model_3d_plain": "stm32g0b1cet6n.glb",+ "model_3d_step": "stm32g0b1cet6n-etched.step",+ "model_3d_step_plain": "stm32g0b1cet6n.step",+ "lbr": "stm32g0b1cet6n.lbr"+ },+ "distributor_links": {+ "lcsc": "C2978903",+ "digikey": "497-STM32G0B1CET6N-ND",+ "mouser": "511-STM32G0B1CET6N"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T06:20:09Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-STM32G0B1CET6N-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "511-STM32G0B1CET6N",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "PC13",+ "type": "bidirectional",+ "description": "FT I/O supplied through the power switch (3 mA sink limit, output max 2 MHz with 30 pF load, not for driving LEDs); AF TIM1_BKIN, additional functions TAMP_IN1, RTC_TS, RTC_OUT1, WKUP2."+ },+ {+ "number": "2",+ "name": "PC14-OSC32_IN",+ "type": "bidirectional",+ "description": "FT I/O supplied through the power switch (limited output use); AF TIM1_BKIN2, additional function OSC32_IN for the 32.768 kHz crystal."+ },+ {+ "number": "3",+ "name": "PC15-OSC32_OUT",+ "type": "bidirectional",+ "description": "FT I/O supplied through the power switch (limited output use); AF OSC32_EN, OSC_EN, TIM15_BKIN, additional function OSC32_OUT for the 32.768 kHz crystal."+ },+ {+ "number": "4",+ "name": "VBAT",+ "type": "power_in",+ "description": "Backup supply (1.55 V to 3.6 V) for RTC, TAMP, LSE oscillator and backup registers when VDD is not present."+ },+ {+ "number": "5",+ "name": "VREF+",+ "type": "power_in",+ "description": "Analog reference voltage input or VREFBUF output (VREFBUF_OUT); must equal VDDA when VDDA < 2 V, otherwise between 2 V and VDDA."+ },+ {+ "number": "6",+ "name": "VDD/VDDA",+ "type": "power_in",+ "description": "Main digital and analog supply, 1.7 V to 3.6 V, also supplies VDDIO1; decouple with 100 nF + 4.7 µF ceramic capacitors."+ },+ {+ "number": "7",+ "name": "VSS/VSSA",+ "type": "power_in",+ "description": "Ground for digital and analog supplies."+ },+ {+ "number": "8",+ "name": "PF0-OSC_IN",+ "type": "bidirectional",+ "description": "FT I/O with AF CRS1_SYNC, EVENTOUT, TIM14_CH1; additional function OSC_IN for the 4-48 MHz crystal oscillator."+ },+ {+ "number": "9",+ "name": "PF1-OSC_OUT",+ "type": "bidirectional",+ "description": "FT I/O with AF OSC_EN, EVENTOUT, TIM15_CH1N; additional function OSC_OUT for the 4-48 MHz crystal oscillator."+ },+ {+ "number": "10",+ "name": "PF2-NRST",+ "type": "bidirectional",+ "description": "Bidirectional reset pin with embedded weak pull-up; also GPIO with AF MCO, LPUART2_TX, LPUART2_RTS_DE."+ },+ {+ "number": "11",+ "name": "PA0",+ "type": "bidirectional",+ "description": "FT_a I/O with AF SPI2_SCK/I2S2_CK, USART2_CTS, TIM2_CH1_ETR, USART4_TX, LPTIM1_OUT, UCPD2_FRSTX, COMP1_OUT; additional COMP1_INM8, ADC_IN0, TAMP_IN2, WKUP1."+ },+ {+ "number": "12",+ "name": "PA1",+ "type": "bidirectional",+ "description": "FT_ea I/O with AF SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK, TIM2_CH2, USART4_RX, TIM15_CH1N, I2C1_SMBA, EVENTOUT; additional COMP1_INP2, ADC_IN1."+ },+ {+ "number": "13",+ "name": "PA2",+ "type": "bidirectional",+ "description": "FT_a I/O with AF SPI1_MOSI/I2S1_SD, USART2_TX, TIM2_CH3, UCPD1_FRSTX, TIM15_CH1, LPUART1_TX, COMP2_OUT; additional COMP2_INM8, ADC_IN2, WKUP4, LSCO."+ },+ {+ "number": "14",+ "name": "PA3",+ "type": "bidirectional",+ "description": "FT_ea I/O with AF SPI2_MISO/I2S2_MCK, USART2_RX, TIM2_CH4, UCPD2_FRSTX, TIM15_CH2, LPUART1_RX, EVENTOUT; additional COMP2_INP2, ADC_IN3."+ },+ {+ "number": "15",+ "name": "PA4",+ "type": "bidirectional",+ "description": "TT_a I/O (3.6 V tolerant) with AF SPI1_NSS/I2S1_WS, SPI2_MOSI/I2S2_SD, USB_NOE, USART6_TX, TIM14_CH1, LPTIM2_OUT, UCPD2_FRSTX, EVENTOUT, SPI3_NSS; additional ADC_IN4, DAC1_OUT1, RTC_OUT2."+ },+ {+ "number": "16",+ "name": "PA5",+ "type": "bidirectional",+ "description": "TT_ea I/O (3.6 V tolerant) with AF SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, USART6_RX, USART3_TX, LPTIM2_ETR, UCPD1_FRSTX, EVENTOUT; additional ADC_IN5, DAC1_OUT2."+ },+ {+ "number": "17",+ "name": "PA6",+ "type": "bidirectional",+ "description": "FT_ea I/O with AF SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN, USART6_CTS, USART3_CTS, TIM16_CH1, LPUART1_CTS, COMP1_OUT, I2C2_SDA, I2C3_SDA; additional ADC_IN6."+ },+ {+ "number": "18",+ "name": "PA7",+ "type": "bidirectional",+ "description": "FT_a I/O with AF SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N, USART6_RTS_DE_CK, TIM14_CH1, TIM17_CH1, UCPD1_FRSTX, COMP2_OUT, I2C2_SCL, I2C3_SCL; additional ADC_IN7."+ },+ {+ "number": "19",+ "name": "PB0",+ "type": "bidirectional",+ "description": "FT_ea I/O with AF SPI1_NSS/I2S1_WS, TIM3_CH3, TIM1_CH2N, FDCAN2_RX, USART3_RX, LPTIM1_OUT, UCPD1_FRSTX, COMP1_OUT, USART5_TX, LPUART2_CTS; additional COMP3_INP0, ADC_IN8."+ },+ {+ "number": "20",+ "name": "PB1",+ "type": "bidirectional",+ "description": "FT_ea I/O with AF TIM14_CH1, TIM3_CH4, TIM1_CH3N, FDCAN2_TX, USART3_RTS_DE_CK, LPTIM2_IN1, LPUART1_RTS_DE, COMP3_OUT, USART5_RX, LPUART2_RTS_DE; additional COMP1_INM6, ADC_IN9."+ },+ {+ "number": "21",+ "name": "PB2",+ "type": "bidirectional",+ "description": "FT_ea I/O with AF SPI2_MISO/I2S2_MCK, MCO2, USART3_TX, LPTIM1_OUT, EVENTOUT; additional COMP1_INP1, COMP3_INM6, ADC_IN10."+ },+ {+ "number": "22",+ "name": "PB10",+ "type": "bidirectional",+ "description": "FT_fa I/O (Fm+ capable) with AF CEC, LPUART1_RX, TIM2_CH3, USART3_TX, SPI2_SCK/I2S2_CK, I2C2_SCL, COMP1_OUT; additional ADC_IN11."+ },+ {+ "number": "23",+ "name": "PB11",+ "type": "bidirectional",+ "description": "FT_fa I/O (Fm+ capable) with AF SPI2_MOSI/I2S2_SD, LPUART1_TX, TIM2_CH4, USART3_RX, I2C2_SDA, COMP2_OUT; additional ADC_IN15."+ },+ {+ "number": "24",+ "name": "PB12",+ "type": "bidirectional",+ "description": "FT_fa I/O (Fm+ capable) with AF SPI2_NSS/I2S2_WS, LPUART1_RTS_DE, TIM1_BKIN, FDCAN2_RX, TIM15_BKIN, UCPD2_FRSTX, EVENTOUT, I2C2_SMBA; additional ADC_IN16."+ },+ {+ "number": "25",+ "name": "PB13",+ "type": "bidirectional",+ "description": "FT_f I/O (Fm+ capable) with AF SPI2_SCK/I2S2_CK, LPUART1_CTS, TIM1_CH1N, FDCAN2_TX, USART3_CTS, TIM15_CH1N, I2C2_SCL, EVENTOUT."+ },+ {+ "number": "26",+ "name": "PB14",+ "type": "bidirectional",+ "description": "FT_f I/O (Fm+ capable) with AF SPI2_MISO/I2S2_MCK, UCPD1_FRSTX, TIM1_CH2N, USART3_RTS_DE_CK, TIM15_CH1, I2C2_SDA, EVENTOUT, USART6_RTS_DE_CK."+ },+ {+ "number": "27",+ "name": "PB15",+ "type": "bidirectional",+ "description": "FT_fc I/O (Fm+, USB Type-C PD capable) with AF SPI2_MOSI/I2S2_SD, TIM1_CH3N, TIM15_CH1N, TIM15_CH2, EVENTOUT, USART6_CTS; additional UCPD1_CC2, RTC_REFIN; may have a pull-down after reset."+ },+ {+ "number": "28",+ "name": "PA8",+ "type": "bidirectional",+ "description": "FT_fc I/O (Fm+, USB Type-C PD capable) with AF MCO, SPI2_NSS/I2S2_WS, TIM1_CH1, CRS1_SYNC, LPTIM2_OUT, EVENTOUT, I2C2_SMBA; additional UCPD1_CC1; may have a pull-down after reset."+ },+ {+ "number": "29",+ "name": "PA9",+ "type": "bidirectional",+ "description": "FT_fd I/O (Fm+, UCPD dead battery) with AF MCO, USART1_TX, TIM1_CH2, SPI2_MISO/I2S2_MCK, TIM15_BKIN, I2C1_SCL, EVENTOUT, I2C2_SCL; additional UCPD1_DBCC1; can be remapped in place of PA11."+ },+ {+ "number": "30",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground pin on the N version, additional to VSS/VSSA."+ },+ {+ "number": "31",+ "name": "VDDIO2",+ "type": "power_in",+ "description": "Independent I/O supply of 1.6 V to 3.6 V for selected I/Os and VDDUSB; must not be applied without valid VDD."+ },+ {+ "number": "32",+ "name": "PA10",+ "type": "bidirectional",+ "description": "FT_fd I/O (Fm+, UCPD dead battery) with AF SPI2_MOSI/I2S2_SD, USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN, I2C1_SDA, EVENTOUT, I2C2_SDA; additional UCPD1_DBCC2; can be remapped in place of PA12."+ },+ {+ "number": "33",+ "name": "PA11 [PA9]",+ "type": "bidirectional",+ "description": "FT_f I/O (Fm+) with AF SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4, FDCAN1_RX, TIM1_BKIN2, I2C2_SCL, COMP1_OUT; additional USB_DM; PA9 can be remapped here via SYSCFG_CFGR1."+ },+ {+ "number": "34",+ "name": "PA12 [PA10]",+ "type": "bidirectional",+ "description": "FT_f I/O (Fm+) with AF SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK, TIM1_ETR, FDCAN1_TX, I2S_CKIN, I2C2_SDA, COMP2_OUT; additional USB_DP; PA10 can be remapped here via SYSCFG_CFGR1."+ },+ {+ "number": "35",+ "name": "PA13",+ "type": "bidirectional",+ "description": "FT_e I/O configured as SWDIO at reset with internal pull-up active; AF IR_OUT, USB_NOE, EVENTOUT, LPUART2_RX."+ },+ {+ "number": "36",+ "name": "PA14-BOOT0",+ "type": "bidirectional",+ "description": "FT I/O configured as SWCLK at reset with internal pull-down active; AF USART2_TX, EVENTOUT, LPUART2_TX; additional function BOOT0."+ },+ {+ "number": "37",+ "name": "PA15",+ "type": "bidirectional",+ "description": "FT I/O with AF SPI1_NSS/I2S1_WS, USART2_RX, TIM2_CH1_ETR, MCO2, USART4_RTS_DE_CK, USART3_RTS_DE_CK, USB_NOE, EVENTOUT, I2C2_SMBA, SPI3_NSS."+ },+ {+ "number": "38",+ "name": "PD0",+ "type": "bidirectional",+ "description": "FT_c I/O (USB Type-C PD capable) with AF EVENTOUT, SPI2_NSS/I2S2_WS, TIM16_CH1, FDCAN1_RX; additional UCPD2_CC1; may have a pull-down after reset."+ },+ {+ "number": "39",+ "name": "PD1",+ "type": "bidirectional",+ "description": "FT_d I/O (UCPD dead battery) with AF EVENTOUT, SPI2_SCK/I2S2_CK, TIM17_CH1, FDCAN1_TX; additional UCPD2_DBCC1; may have a pull-down after reset."+ },+ {+ "number": "40",+ "name": "PD2",+ "type": "bidirectional",+ "description": "FT_c I/O (USB Type-C PD capable) with AF USART3_RTS_DE_CK, TIM3_ETR, TIM1_CH1N, USART5_RX; additional UCPD2_CC2; may have a pull-down after reset."+ },+ {+ "number": "41",+ "name": "PD3",+ "type": "bidirectional",+ "description": "FT_d I/O (UCPD dead battery) with AF USART2_CTS, SPI2_MISO/I2S2_MCK, TIM1_CH2N, USART5_TX; additional UCPD2_DBCC2; may have a pull-down after reset."+ },+ {+ "number": "42",+ "name": "PB3",+ "type": "bidirectional",+ "description": "FT_a I/O with AF SPI1_SCK/I2S1_CK, TIM1_CH2, TIM2_CH2, USART5_TX, USART1_RTS_DE_CK, I2C3_SCL, EVENTOUT, I2C2_SCL, SPI3_SCK; additional COMP2_INM6."+ },+ {+ "number": "43",+ "name": "PB4",+ "type": "bidirectional",+ "description": "FT_a I/O with AF SPI1_MISO/I2S1_MCK, TIM3_CH1, USART5_RX, USART1_CTS, TIM17_BKIN, I2C3_SDA, EVENTOUT, I2C2_SDA, SPI3_MISO; additional COMP2_INP0."+ },+ {+ "number": "44",+ "name": "PB5",+ "type": "bidirectional",+ "description": "FT I/O with AF SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM16_BKIN, FDCAN2_RX, LPTIM1_IN1, I2C1_SMBA, COMP2_OUT, USART5_RTS_DE_CK, SPI3_MOSI; additional WKUP6."+ },+ {+ "number": "45",+ "name": "PB6",+ "type": "bidirectional",+ "description": "FT_fa I/O (Fm+ capable) with AF USART1_TX, TIM1_CH3, TIM16_CH1N, FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR, I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1, LPUART2_TX; additional COMP2_INP1."+ },+ {+ "number": "46",+ "name": "PB7",+ "type": "bidirectional",+ "description": "FT_fa I/O (Fm+ capable) with AF USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N, USART4_CTS, LPTIM1_IN2, I2C1_SDA, EVENTOUT, TIM4_CH2, LPUART2_RX; additional COMP2_INM7, PVD_IN."+ },+ {+ "number": "47",+ "name": "PB8",+ "type": "bidirectional",+ "description": "FT_f I/O (Fm+ capable) with AF CEC, SPI2_SCK/I2S2_CK, TIM16_CH1, FDCAN1_RX, USART3_TX, TIM15_BKIN, I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3."+ },+ {+ "number": "48",+ "name": "PB9",+ "type": "bidirectional",+ "description": "FT_f I/O (Fm+ capable) with AF IR_OUT, UCPD2_FRSTX, TIM17_CH1, FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS, I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: PC13, PC14, PC15 are in RTC domain with limited drive capability (3 mA max, 2 MHz max speed) - verif; PA11/PA12 and PA9/PA10 pins can be remapped using SYSCFG_CFGR1 register for USB_DM/USB_DP assignment; VDDIO2 pin (30) is independent supply requiring separate decoupling; VSS at pin 31 is located mid-pa"+ ],+ "pages_sent": 85,+ "cost_usd": 0.5643,+ "at": "2026-10-01T06:19:46"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589836521785630720",+ "pages": 159,+ "sha256": "ee33614bd414ac41",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 48,+ "described": 48,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}