STM32F411RET6

@@ -0,0 +1,112 @@+# STM32F411RET6++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)++STM32F411RET6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VBAT | power_in | Battery backup supply for the RTC, LSE 32 kHz oscillator, and backup registers when VDD is off. 1.65 V to 3.6 V. Tie to VDD if backup domain is not used. |+| 2 | PC13-ANTI_TAMP | bidirectional | GPIO PC13 in the VBAT backup domain, also RTC anti-tamper input, RTC alarm/calibration output, and RTC timestamp input. Powered from VBAT switch, so output drive is limited (~3 mA, 2 MHz, 30 pF max). |+| 3 | PC14-OSC32_IN | bidirectional | GPIO PC14, or LSE 32.768 kHz crystal input (OSC32_IN) for the RTC. Backup domain; not 5 V tolerant when used in oscillator/analog mode. |+| 4 | PC15-OSC32_OUT | bidirectional | GPIO PC15, or LSE 32.768 kHz crystal output (OSC32_OUT) for the RTC. Backup domain; not 5 V tolerant when used in oscillator/analog mode. |+| 5 | PH0-OSC_IN | bidirectional | GPIO PH0, or HSE 4-26 MHz main crystal oscillator input (OSC_IN). Not 5 V tolerant in oscillator/analog mode. |+| 6 | PH1-OSC_OUT | bidirectional | GPIO PH1, or HSE 4-26 MHz main crystal oscillator output (OSC_OUT). Not 5 V tolerant in oscillator/analog mode. |+| 7 | NRST | bidirectional | Bidirectional device reset with embedded weak pull-up (~40 kΩ). Active low; drive low to reset the MCU. |+| 8 | PC0 | bidirectional | General-purpose I/O PC0, 5 V-tolerant. Alt: EVENTOUT. Additional function: ADC1_IN10. |+| 9 | PC1 | bidirectional | General-purpose I/O PC1, 5 V-tolerant. Alt: EVENTOUT. Additional function: ADC1_IN11. |+| 10 | PC2 | bidirectional | General-purpose I/O PC2, 5 V-tolerant. Alt: SPI2_MISO, I2S2ext_SD, EVENTOUT. Additional: ADC1_IN12. |+| 11 | PC3 | bidirectional | General-purpose I/O PC3, 5 V-tolerant. Alt: SPI2_MOSI/I2S2_SD, EVENTOUT. Additional: ADC1_IN13. |+| 12 | VSSA | power_in | Analog ground reference for the ADC and analog supply. Connect to the board analog ground plane. |+| 13 | VREF+/VDDA | power_in | In LQFP64, VREF+ and VDDA share pin 13 as the analog supply / ADC positive reference. 1.7-3.6 V (min 1.8 V for full ADC accuracy). |+| 14 | PA0-WKUP | bidirectional | GPIO PA0 (TC 3.3 V pad) with system wake-up capability. Alt: TIM2_CH1/TIM2_ETR, TIM5_CH1, USART2_CTS, EVENTOUT. Additional: ADC1_IN0, WKUP1. |+| 15 | PA1 | bidirectional | GPIO PA1, 5 V-tolerant. Alt: TIM2_CH2, TIM5_CH2, SPI4_MOSI/I2S4_SD, USART2_RTS, EVENTOUT. Additional: ADC1_IN1. |+| 16 | PA2 | bidirectional | GPIO PA2, 5 V-tolerant. Alt: TIM2_CH3, TIM5_CH3, TIM9_CH1, I2S2_CKIN, USART2_TX, EVENTOUT. Additional: ADC1_IN2. |+| 17 | PA3 | bidirectional | GPIO PA3, 5 V-tolerant. Alt: TIM2_CH4, TIM5_CH4, TIM9_CH2, I2S2_MCK, USART2_RX, EVENTOUT. Additional: ADC1_IN3. |+| 18 | VSS | power_in | Digital ground reference. Connect to board ground. |+| 19 | VDD | power_in | Digital supply, 1.7 V to 3.6 V. Decouple with a 100 nF cap close to the pin. |+| 20 | PA4 | bidirectional | GPIO PA4, 5 V-tolerant. Alt: SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, EVENTOUT. Additional: ADC1_IN4. |+| 21 | PA5 | bidirectional | GPIO PA5, 5 V-tolerant. Alt: TIM2_CH1/TIM2_ETR, SPI1_SCK/I2S1_CK, EVENTOUT. Additional: ADC1_IN5. |+| 22 | PA6 | bidirectional | GPIO PA6, 5 V-tolerant. Alt: TIM1_BKIN, TIM3_CH1, SPI1_MISO, I2S2_MCK, SDIO_CMD, EVENTOUT. Additional: ADC1_IN6. |+| 23 | PA7 | bidirectional | GPIO PA7, 5 V-tolerant. Alt: TIM1_CH1N, TIM3_CH2, SPI1_MOSI/I2S1_SD, EVENTOUT. Additional: ADC1_IN7. |+| 24 | PC4 | bidirectional | GPIO PC4, 5 V-tolerant. Alt: EVENTOUT. Additional: ADC1_IN14. |+| 25 | PC5 | bidirectional | GPIO PC5, 5 V-tolerant. Alt: EVENTOUT. Additional: ADC1_IN15. |+| 26 | PB0 | bidirectional | GPIO PB0, 5 V-tolerant. Alt: TIM1_CH2N, TIM3_CH3, SPI5_SCK/I2S5_CK, EVENTOUT. Additional: ADC1_IN8. |+| 27 | PB1 | bidirectional | GPIO PB1, 5 V-tolerant. Alt: TIM1_CH3N, TIM3_CH4, SPI5_NSS/I2S5_WS, EVENTOUT. Additional: ADC1_IN9. |+| 28 | PB2/BOOT1 | bidirectional | GPIO PB2, 5 V-tolerant, also latched at reset as BOOT1 to (with BOOT0) select the boot memory (main Flash, system memory or SRAM). |+| 29 | PB10 | bidirectional | GPIO PB10, 5 V-tolerant. Alt: TIM2_CH3, I2C2_SCL, SPI2_SCK/I2S2_CK, I2S3_MCK, SDIO_D7, EVENTOUT. |+| 30 | VCAP_1 | passive | Internal 1.2 V regulator decoupling output. Connect a 2.2 µF low-ESR ceramic capacitor to VSS. Do not drive. |+| 31 | VSS | power_in | Digital ground reference. |+| 32 | VDD | power_in | Digital supply, 1.7 V to 3.6 V. Decouple with 100 nF close to the pin. |+| 33 | PB12 | bidirectional | GPIO PB12, 5 V-tolerant. Alt: TIM1_BKIN, I2C2_SMBA, SPI2_NSS/I2S2_WS, SPI4_NSS/I2S4_WS, SPI3_SCK/I2S3_CK, EVENTOUT. |+| 34 | PB13 | bidirectional | GPIO PB13, 5 V-tolerant. Alt: TIM1_CH1N, SPI2_SCK/I2S2_CK, SPI4_SCK/I2S4_CK, EVENTOUT. |+| 35 | PB14 | bidirectional | GPIO PB14, 5 V-tolerant. Alt: TIM1_CH2N, SPI2_MISO, I2S2ext_SD, SDIO_D6, EVENTOUT. |+| 36 | PB15 | bidirectional | GPIO PB15, 5 V-tolerant. Alt: RTC_50Hz, TIM1_CH3N, SPI2_MOSI/I2S2_SD, SDIO_CK, EVENTOUT. Additional: RTC_REFIN. |+| 37 | PC6 | bidirectional | GPIO PC6, 5 V-tolerant. Alt: TIM3_CH1, I2S2_MCK, USART6_TX, SDIO_D6, EVENTOUT. |+| 38 | PC7 | bidirectional | GPIO PC7, 5 V-tolerant. Alt: TIM3_CH2, SPI2_SCK/I2S2_CK, I2S3_MCK, USART6_RX, SDIO_D7, EVENTOUT. |+| 39 | PC8 | bidirectional | GPIO PC8, 5 V-tolerant. Alt: TIM3_CH3, USART6_CK, SDIO_D0, EVENTOUT. |+| 40 | PC9 | bidirectional | GPIO PC9, 5 V-tolerant. Alt: MCO_2, TIM3_CH4, I2C3_SDA, I2S2_CKIN, SDIO_D1, EVENTOUT. |+| 41 | PA8 | bidirectional | GPIO PA8, 5 V-tolerant. Alt: MCO_1, TIM1_CH1, I2C3_SCL, USART1_CK, USB_FS_SOF, SDIO_D1, EVENTOUT. |+| 42 | PA9 | bidirectional | GPIO PA9, 5 V-tolerant. Alt: TIM1_CH2, I2C3_SMBA, USART1_TX, USB_FS_VBUS, SDIO_D2, EVENTOUT. Additional: OTG_FS_VBUS sense input. |+| 43 | PA10 | bidirectional | GPIO PA10, 5 V-tolerant. Alt: TIM1_CH3, SPI5_MOSI/I2S5_SD, USART1_RX, USB_FS_ID, EVENTOUT. |+| 44 | PA11 | bidirectional | GPIO PA11, 5 V-tolerant. USB full-speed D- (USB_FS_DM). Alt: TIM1_CH4, SPI4_MISO, USART1_CTS, USART6_TX, EVENTOUT. |+| 45 | PA12 | bidirectional | GPIO PA12, 5 V-tolerant. USB full-speed D+ (USB_FS_DP). Alt: TIM1_ETR, SPI5_MISO, USART1_RTS, USART6_RX, EVENTOUT. |+| 46 | PA13/JTMS-SWDIO | bidirectional | GPIO PA13, 5 V-tolerant. Default alt after reset: JTMS/SWDIO (Serial Wire Debug data or JTAG test mode select). Alt: EVENTOUT. |+| 47 | VSS | power_in | Digital ground reference. |+| 48 | VDD | power_in | Digital supply, 1.7 V to 3.6 V. Decouple with 100 nF close to the pin. |+| 49 | PA14/JTCK-SWCLK | bidirectional | GPIO PA14, 5 V-tolerant. Default alt after reset: JTCK/SWCLK (Serial Wire Debug clock or JTAG test clock). Alt: EVENTOUT. |+| 50 | PA15/JTDI | bidirectional | GPIO PA15, 5 V-tolerant. Default alt after reset: JTDI (JTAG test data in). Alt: TIM2_CH1/TIM2_ETR, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART1_TX, EVENTOUT. |+| 51 | PC10 | bidirectional | GPIO PC10, 5 V-tolerant. Alt: SPI3_SCK/I2S3_CK, SDIO_D2, EVENTOUT. |+| 52 | PC11 | bidirectional | GPIO PC11, 5 V-tolerant. Alt: I2S3ext_SD, SPI3_MISO, SDIO_D3, EVENTOUT. |+| 53 | PC12 | bidirectional | GPIO PC12, 5 V-tolerant. Alt: SPI3_MOSI/I2S3_SD, SDIO_CK, EVENTOUT. |+| 54 | PD2 | bidirectional | GPIO PD2, 5 V-tolerant. Alt: TIM3_ETR, SDIO_CMD, EVENTOUT. |+| 55 | PB3/JTDO-SWO | bidirectional | GPIO PB3, 5 V-tolerant. Default alt after reset: JTDO/TRACESWO (JTAG test data out / Serial Wire trace). Alt: TIM2_CH2, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART1_RX, I2C2_SDA, EVENTOUT. |+| 56 | PB4/JTRST | bidirectional | GPIO PB4, 5 V-tolerant. Default alt after reset: NJTRST (JTAG test reset, active low). Alt: TIM3_CH1, SPI1_MISO, SPI3_MISO, I2S3ext_SD, I2C3_SDA, SDIO_D0, EVENTOUT. |+| 57 | PB5 | bidirectional | GPIO PB5 (TC 3.3 V pad). Alt: TIM3_CH2, I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, SDIO_D3, EVENTOUT. |+| 58 | PB6 | bidirectional | GPIO PB6, 5 V-tolerant. Alt: TIM4_CH1, I2C1_SCL, USART1_TX, EVENTOUT. |+| 59 | PB7 | bidirectional | GPIO PB7, 5 V-tolerant. Alt: TIM4_CH2, I2C1_SDA, USART1_RX, SDIO_D0, EVENTOUT. |+| 60 | BOOT0 | input | Boot-mode select input (dedicated pad, no GPIO function). Sampled at reset with BOOT1 (PB2) to choose the boot memory: main Flash, system bootloader, or embedded SRAM. Additional: VPP (Flash programming). |+| 61 | PB8 | bidirectional | GPIO PB8, 5 V-tolerant. Alt: TIM4_CH3, TIM10_CH1, I2C1_SCL, SPI5_MOSI/I2S5_SD, I2C3_SDA, SDIO_D4, EVENTOUT. |+| 62 | PB9 | bidirectional | GPIO PB9, 5 V-tolerant. Alt: TIM4_CH4, TIM11_CH1, I2C1_SDA, SPI2_NSS/I2S2_WS, I2C2_SDA, SDIO_D5, EVENTOUT. |+| 63 | VSS | power_in | Digital ground reference. |+| 64 | VDD | power_in | Digital supply, 1.7 V to 3.6 V. Decouple with 100 nF close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-64(10x10) |+| Category | MCU |+| Pins | 64 |++## Ordering variants++- `STM32F411RET6RCT6`+- `STM32F411RET6RET6`+- `STM32F411RET6VCT6`+- `STM32F411RET6VET6`+- `STM32F411RET6CCU6`+- `STM32F411RET6CEU6`+- `STM32F411RET6CCY6TR`+- `STM32F411RET6CEY6TR`+- `STM32F411RET6VCH6`+- `STM32F411RET6VEH6`++## CAD (KiCad official)++- Symbol: `STM32F411RET6`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/stm32f411ret6.pdf) (149 pp, sha256 `b9ea11576a10fd6f`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stm32f411ret6-datasheet.pdf)