component
STM32F373RCT6
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.
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README.mdadded+100@@ -0,0 +1,100 @@+# STM32F373RCT6++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)++STM32F373RCT6 from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model, then checked against ST open pin data); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VBAT | power_in | Backup power supply for the RTC and backup registers (VBAT supply). |+| 2 | PC13 | bidirectional | Standard 3.3 V I/O (TC) supplied through the power switch, which sinks only 3 mA, so output speed must not exceed 2 MHz at 30 pF max load and the pin must not source current such as driving an LED; also WKUP2, ALARM_OUT, CALIB_OUT, TIMESTAMP, RTC_TAMPER1. |+| 3 | PC14 | bidirectional | Standard 3.3 V I/O (TC) supplied through the power switch with the same 3 mA limit and output restrictions as PC13; default function OSC32_IN (32 kHz oscillator input). |+| 4 | PC15 | bidirectional | Standard 3.3 V I/O (TC) supplied through the power switch with the same 3 mA limit and output restrictions as PC13; default function OSC32_OUT (32 kHz oscillator output). |+| 5 | PF0 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); default function OSC_IN (4 to 32 MHz crystal input), alternate function I2C2_SDA. |+| 6 | PF1 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); default function OSC_OUT (4 to 32 MHz crystal output), alternate function I2C2_SCL. |+| 7 | NRST | bidirectional | Bidirectional active-low device reset input / internal reset output with embedded weak pull-up resistor. |+| 8 | PC0 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate TIM5_CH1_ETR, additional function ADC_IN10. |+| 9 | PC1 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate TIM5_CH2, additional function ADC_IN11. |+| 10 | PC2 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI2_MISO/I2S2_MCK and TIM5_CH3, additional function ADC_IN12. |+| 11 | PC3 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI2_MOSI/I2S2_SD and TIM5_CH4, additional function ADC_IN13. |+| 12 | VSSA/VREF- | power_in | Analog ground and negative reference voltage for the ADC, COMP and DAC. |+| 13 | VDDA | power_in | Analog power supply for the ADC, COMP and DAC; the 12-bit ADC analog supply is specified as 2.4 to 3.6 V. |+| 14 | PA0 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate USART2_CTS, TIM2_CH1_ETR, TIM5_CH1_ETR, TIM19_CH1, TSC_G1_IO1, COMP1_OUT; additional RTC_TAMPER2, WKUP1, ADC_IN0, COMP1_INM. |+| 15 | PA1 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI3_SCK/I2S3_CK, USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, RTC_REFIN; additional ADC_IN1, COMP1_INP. |+| 16 | PA2 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate COMP2_OUT, SPI3_MISO/I2S3_MCK, USART2_TX, TIM2_CH3, TIM15_CH1, TSC_G1_IO3; additional ADC_IN2, COMP2_INM. |+| 17 | VREF+ | power_in | Positive reference voltage for the ADC, COMP and DAC. |+| 18 | PA3 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI3_MOSI/I2S3_SD, USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4; additional ADC_IN3, COMP2_INP. |+| 19 | VDD_2 | power_in | Digital power supply; the device operating voltage range is 2.0 to 3.6 V. |+| 20 | PA4 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, TIM3_CH2, TIM12_CH1, TSC_G2_IO1; additional ADC_IN4, DAC1_OUT1. |+| 21 | PA5 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, TIM14_CH1, TIM12_CH2, TSC_G2_IO2; additional ADC_IN5, DAC1_OUT2. |+| 22 | PA6 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI1_MISO/I2S1_MCK, COMP1_OUT, TIM3_CH1, TIM13_CH1, TIM16_CH1, TSC_G2_IO3; additional ADC_IN6, DAC2_OUT1. |+| 23 | PA7 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa), with reduced touch sensing sensitivity; alternate TSC_G2_IO4, TIM14_CH1, SPI1_MOSI/I2S1_SD, TIM17_CH1, TIM3_CH2, COMP2_OUT; additional ADC_IN7. |+| 24 | PC4 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate TIM13_CH1, TSC_G3_IO1, USART1_TX; additional ADC_IN14. |+| 25 | PC5 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate TSC_G3_IO2, USART1_RX; additional ADC_IN15. |+| 26 | PB0 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI1_MOSI/I2S1_SD, TIM3_CH3, TSC_G3_IO3, TIM3_CH2; additional ADC_IN8, SDADC1_AIN6P. |+| 27 | PB1 | bidirectional | 3.3 V tolerant I/O directly connected to ADC (TTa); alternate TIM3_CH4, TSC_G3_IO4; additional ADC_IN9, SDADC1_AIN5P, SDADC1_AIN6M. |+| 28 | PB2 | bidirectional | Standard 3.3 V I/O (TC) powered by VDDSD12; additional functions SDADC1_AIN4P and SDADC2_AIN6P. |+| 29 | PE8 | bidirectional | Standard 3.3 V I/O (TC) powered by VDDSD12; additional functions SDADC1_AIN8P and SDADC2_AIN8P. |+| 30 | PE9 | bidirectional | Standard 3.3 V I/O (TC) powered by VDDSD12; additional functions SDADC1_AIN7P, SDADC1_AIN8M, SDADC2_AIN7P and SDADC2_AIN8M. |+| 31 | VSSSD/VREFSD- | power_in | Ground for SDADC1, SDADC2 and SDADC3, and external reference voltage input (negative) also used as negative SDADC analog input in single-ended mode. |+| 32 | VDDSD | power_in | Power supply for SDADC1, SDADC2 and SDADC3. |+| 33 | VREFSD+ | power_in | External reference voltage (positive input) for SDADC1, SDADC2 and SDADC3. |+| 34 | PB14 | bidirectional | Standard 3.3 V I/O (TC) powered by VDDSD3; alternate SPI2_MISO/I2S2_MCK, USART3_RTS, TIM15_CH1, TIM12_CH1, TSC_G6_IO1; additional SDADC3_AIN8P. |+| 35 | PB15 | bidirectional | Standard 3.3 V I/O (TC) powered by VDDSD3; alternate SPI2_MOSI/I2S2_SD, TIM15_CH1N, TIM15_CH2, TIM12_CH2, TSC_G6_IO2, RTC_REFIN; additional SDADC3_AIN7P and SDADC3_AIN8M. |+| 36 | PD8 | bidirectional | Standard 3.3 V I/O (TC) powered by VDDSD3; alternate SPI2_SCK/I2S2_CK, USART3_TX, TSC_G6_IO3; additional SDADC3_AIN6P. |+| 37 | PC6 | bidirectional | 5 V tolerant I/O (FT); alternate TIM3_CH1 and SPI1_NSS/I2S1_WS. |+| 38 | PC7 | bidirectional | 5 V tolerant I/O (FT); alternate TIM3_CH2 and SPI1_SCK/I2S1_CK. |+| 39 | PC8 | bidirectional | 5 V tolerant I/O (FT); alternate SPI1_MISO/I2S1_MCK and TIM3_CH3. |+| 40 | PC9 | bidirectional | 5 V tolerant I/O (FT); alternate SPI1_MOSI/I2S1_SD and TIM3_CH4. |+| 41 | PA8 | bidirectional | 5 V tolerant I/O (FT); alternate MCO, SPI2_SCK/I2S2_CK, I2C2_SMBA, USART1_CK, TIM4_ETR, TIM5_CH1_ETR. |+| 42 | PA9 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); alternate I2C2_SCL, USART1_TX, SPI2_MISO/I2S2_MCK, TIM2_CH3, TIM15_BKIN, TIM13_CH1, TSC_G4_IO1. |+| 43 | PA10 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); alternate I2C2_SDA, USART1_RX, SPI2_MOSI/I2S2_SD, TIM2_CH4, TIM17_BKIN, TIM14_CH1, TSC_G4_IO2. |+| 44 | PA11 | bidirectional | 5 V tolerant I/O (FT); alternate CAN_RX, USB_DM, USART1_CTS, SPI2_NSS/I2S2_WS, SPI1_NSS/I2S1_WS, TIM4_CH1, TIM5_CH2, COMP1_OUT. |+| 45 | PA12 | bidirectional | 5 V tolerant I/O (FT); alternate CAN_TX, USB_DP, USART1_RTS, SPI1_SCK/I2S1_CK, TIM16_CH1, TIM4_CH2, TIM5_CH3, COMP2_OUT. |+| 46 | PA13 | bidirectional | 5 V tolerant I/O (FT); default debug function SWDIO-JTMS, alternate IR_OUT, USART3_CTS, SPI1_MISO/I2S1_MCK, TIM16_CH1N, TIM4_CH3, TIM5_CH4, TSC_G4_IO3. |+| 47 | PF6 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); alternate I2C2_SCL, SPI1_MOSI/I2S1_SD, USART3_RTS, TIM4_CH4. |+| 48 | PF7 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); alternate I2C2_SDA and USART2_CK. |+| 49 | PA14 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); default debug function SWCLK-JTCK, alternate I2C1_SDA, TIM12_CH1, TSC_G4_IO4. |+| 50 | PA15 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); default debug function JTDI, alternate I2C1_SCL, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, TIM2_CH1_ETR, TIM12_CH2, TSC_SYNC. |+| 51 | PC10 | bidirectional | 5 V tolerant I/O (FT); alternate SPI3_SCK/I2S3_CK, USART3_TX, TIM19_CH1. |+| 52 | PC11 | bidirectional | 5 V tolerant I/O (FT); alternate SPI3_MISO/I2S3_MCK, USART3_RX, TIM19_CH2. |+| 53 | PC12 | bidirectional | 5 V tolerant I/O (FT); alternate SPI3_MOSI/I2S3_SD, USART3_CK, TIM19_CH3. |+| 54 | PD2 | bidirectional | 5 V tolerant I/O (FT); alternate TIM3_ETR. |+| 55 | PB3 | bidirectional | 5 V tolerant I/O (FT); default debug function JTDO-TRACESWO, alternate SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART2_TX, TIM2_CH2, TIM3_ETR, TIM4_ETR, TIM13_CH1, TSC_G5_IO1. |+| 56 | PB4 | bidirectional | 5 V tolerant I/O (FT); default function NJTRST, alternate SPI1_MISO/I2S1_MCK, SPI3_MISO/I2S3_MCK, USART2_RX, TIM16_CH1, TIM3_CH1, TIM17_BKIN, TIM15_CH1N, TSC_G5_IO2. |+| 57 | PB5 | bidirectional | 5 V tolerant I/O (FT); alternate I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, USART2_CK, TIM16_BKIN, TIM3_CH2, TIM17_CH1, TIM19_ETR. |+| 58 | PB6 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); alternate I2C1_SCL, USART1_TX, TIM16_CH1N, TIM3_CH3, TIM4_CH1, TIM19_CH1, TIM15_CH1, TSC_G5_IO3. |+| 59 | PB7 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); alternate I2C1_SDA, USART1_RX, TIM17_CH1N, TIM3_CH4, TIM4_CH2, TIM19_CH2, TIM15_CH2, TSC_G5_IO4. |+| 60 | BOOT0 | input | Dedicated BOOT0 input pin used for boot memory selection. |+| 61 | PB8 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); alternate I2C1_SCL, SPI2_SCK/I2S2_CK, CEC, USART3_TX, CAN_RX, TIM16_CH1, TIM4_CH3, TIM19_CH3, COMP1_OUT, TSC_SYNC. |+| 62 | PB9 | bidirectional | 5 V tolerant I/O with FM+ capability (FTf); alternate I2C1_SDA, SPI2_NSS/I2S2_WS, IR_OUT, USART3_RX, CAN_TX, TIM17_CH1, TIM4_CH4, TIM19_CH4, COMP2_OUT. |+| 63 | VSS_1 | power_in | Digital ground. |+| 64 | VDD_1 | power_in | Digital power supply; the device operating voltage range is 2.0 to 3.6 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-64(10x10) |+| Category | Embedded Processors & Controllers |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `STM32F373RCT6`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `stm32f373rct6-etched.step` / `stm32f373rct6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stm32f373rct6.step` / `stm32f373rct6.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586176370364203008) (137 pp, sha256 `fd00ebf096b21764`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stm32f373rct6-datasheet.pdf)
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Pinout checked against ST's open pin data, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "stm32f373rct6",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "stm32f373rct6.kicad_sym",+ "stm32f373rct6.kicad_mod",+ "stm32f373rct6.glb",+ "stm32f373rct6.step",+ "stm32f373rct6.lbr",+ "docs/hero.png",+ "docs/stm32f373rct6-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "stm32f373rct6-hero.glb",+ "stm32f373rct6-hero.overlay.json"+ ],+ "component": {+ "mpn": "STM32F373RCT6",+ "manufacturer": "STMicroelectronics",+ "package": "LQFP-64(10x10)",+ "pin_count": 64,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586176370364203008",+ "parts": {+ "symbol": "stm32f373rct6.kicad_sym",+ "footprint": "stm32f373rct6.kicad_mod",+ "model_3d": "stm32f373rct6-hero.glb",+ "model_3d_plain": "stm32f373rct6.glb",+ "model_3d_step": "stm32f373rct6-etched.step",+ "model_3d_step_plain": "stm32f373rct6.step",+ "lbr": "stm32f373rct6.lbr"+ },+ "distributor_links": {+ "lcsc": "C84174",+ "digikey": "497-13252-ND",+ "mouser": "511-STM32F373RCT6"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T23:17:23Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-13252-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "511-STM32F373RCT6",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VBAT",+ "type": "power_in",+ "description": "Backup power supply for the RTC and backup registers (VBAT supply)."+ },+ {+ "number": "2",+ "name": "PC13",+ "type": "bidirectional",+ "description": "Standard 3.3 V I/O (TC) supplied through the power switch, which sinks only 3 mA, so output speed must not exceed 2 MHz at 30 pF max load and the pin must not source current such as driving an LED; also WKUP2, ALARM_OUT, CALIB_OUT, TIMESTAMP, RTC_TAMPER1."+ },+ {+ "number": "3",+ "name": "PC14",+ "type": "bidirectional",+ "description": "Standard 3.3 V I/O (TC) supplied through the power switch with the same 3 mA limit and output restrictions as PC13; default function OSC32_IN (32 kHz oscillator input)."+ },+ {+ "number": "4",+ "name": "PC15",+ "type": "bidirectional",+ "description": "Standard 3.3 V I/O (TC) supplied through the power switch with the same 3 mA limit and output restrictions as PC13; default function OSC32_OUT (32 kHz oscillator output)."+ },+ {+ "number": "5",+ "name": "PF0",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); default function OSC_IN (4 to 32 MHz crystal input), alternate function I2C2_SDA."+ },+ {+ "number": "6",+ "name": "PF1",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); default function OSC_OUT (4 to 32 MHz crystal output), alternate function I2C2_SCL."+ },+ {+ "number": "7",+ "name": "NRST",+ "type": "bidirectional",+ "description": "Bidirectional active-low device reset input / internal reset output with embedded weak pull-up resistor."+ },+ {+ "number": "8",+ "name": "PC0",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate TIM5_CH1_ETR, additional function ADC_IN10."+ },+ {+ "number": "9",+ "name": "PC1",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate TIM5_CH2, additional function ADC_IN11."+ },+ {+ "number": "10",+ "name": "PC2",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI2_MISO/I2S2_MCK and TIM5_CH3, additional function ADC_IN12."+ },+ {+ "number": "11",+ "name": "PC3",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI2_MOSI/I2S2_SD and TIM5_CH4, additional function ADC_IN13."+ },+ {+ "number": "12",+ "name": "VSSA/VREF-",+ "type": "power_in",+ "description": "Analog ground and negative reference voltage for the ADC, COMP and DAC."+ },+ {+ "number": "13",+ "name": "VDDA",+ "type": "power_in",+ "description": "Analog power supply for the ADC, COMP and DAC; the 12-bit ADC analog supply is specified as 2.4 to 3.6 V."+ },+ {+ "number": "14",+ "name": "PA0",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate USART2_CTS, TIM2_CH1_ETR, TIM5_CH1_ETR, TIM19_CH1, TSC_G1_IO1, COMP1_OUT; additional RTC_TAMPER2, WKUP1, ADC_IN0, COMP1_INM."+ },+ {+ "number": "15",+ "name": "PA1",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI3_SCK/I2S3_CK, USART2_RTS, TIM2_CH2, TIM15_CH1N, TSC_G1_IO2, RTC_REFIN; additional ADC_IN1, COMP1_INP."+ },+ {+ "number": "16",+ "name": "PA2",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate COMP2_OUT, SPI3_MISO/I2S3_MCK, USART2_TX, TIM2_CH3, TIM15_CH1, TSC_G1_IO3; additional ADC_IN2, COMP2_INM."+ },+ {+ "number": "17",+ "name": "VREF+",+ "type": "power_in",+ "description": "Positive reference voltage for the ADC, COMP and DAC."+ },+ {+ "number": "18",+ "name": "PA3",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI3_MOSI/I2S3_SD, USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4; additional ADC_IN3, COMP2_INP."+ },+ {+ "number": "19",+ "name": "VDD_2",+ "type": "power_in",+ "description": "Digital power supply; the device operating voltage range is 2.0 to 3.6 V."+ },+ {+ "number": "20",+ "name": "PA4",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, TIM3_CH2, TIM12_CH1, TSC_G2_IO1; additional ADC_IN4, DAC1_OUT1."+ },+ {+ "number": "21",+ "name": "PA5",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI1_SCK/I2S1_CK, CEC, TIM2_CH1_ETR, TIM14_CH1, TIM12_CH2, TSC_G2_IO2; additional ADC_IN5, DAC1_OUT2."+ },+ {+ "number": "22",+ "name": "PA6",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI1_MISO/I2S1_MCK, COMP1_OUT, TIM3_CH1, TIM13_CH1, TIM16_CH1, TSC_G2_IO3; additional ADC_IN6, DAC2_OUT1."+ },+ {+ "number": "23",+ "name": "PA7",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa), with reduced touch sensing sensitivity; alternate TSC_G2_IO4, TIM14_CH1, SPI1_MOSI/I2S1_SD, TIM17_CH1, TIM3_CH2, COMP2_OUT; additional ADC_IN7."+ },+ {+ "number": "24",+ "name": "PC4",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate TIM13_CH1, TSC_G3_IO1, USART1_TX; additional ADC_IN14."+ },+ {+ "number": "25",+ "name": "PC5",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate TSC_G3_IO2, USART1_RX; additional ADC_IN15."+ },+ {+ "number": "26",+ "name": "PB0",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate SPI1_MOSI/I2S1_SD, TIM3_CH3, TSC_G3_IO3, TIM3_CH2; additional ADC_IN8, SDADC1_AIN6P."+ },+ {+ "number": "27",+ "name": "PB1",+ "type": "bidirectional",+ "description": "3.3 V tolerant I/O directly connected to ADC (TTa); alternate TIM3_CH4, TSC_G3_IO4; additional ADC_IN9, SDADC1_AIN5P, SDADC1_AIN6M."+ },+ {+ "number": "28",+ "name": "PB2",+ "type": "bidirectional",+ "description": "Standard 3.3 V I/O (TC) powered by VDDSD12; additional functions SDADC1_AIN4P and SDADC2_AIN6P."+ },+ {+ "number": "29",+ "name": "PE8",+ "type": "bidirectional",+ "description": "Standard 3.3 V I/O (TC) powered by VDDSD12; additional functions SDADC1_AIN8P and SDADC2_AIN8P."+ },+ {+ "number": "30",+ "name": "PE9",+ "type": "bidirectional",+ "description": "Standard 3.3 V I/O (TC) powered by VDDSD12; additional functions SDADC1_AIN7P, SDADC1_AIN8M, SDADC2_AIN7P and SDADC2_AIN8M."+ },+ {+ "number": "31",+ "name": "VSSSD/VREFSD-",+ "type": "power_in",+ "description": "Ground for SDADC1, SDADC2 and SDADC3, and external reference voltage input (negative) also used as negative SDADC analog input in single-ended mode."+ },+ {+ "number": "32",+ "name": "VDDSD",+ "type": "power_in",+ "description": "Power supply for SDADC1, SDADC2 and SDADC3."+ },+ {+ "number": "33",+ "name": "VREFSD+",+ "type": "power_in",+ "description": "External reference voltage (positive input) for SDADC1, SDADC2 and SDADC3."+ },+ {+ "number": "34",+ "name": "PB14",+ "type": "bidirectional",+ "description": "Standard 3.3 V I/O (TC) powered by VDDSD3; alternate SPI2_MISO/I2S2_MCK, USART3_RTS, TIM15_CH1, TIM12_CH1, TSC_G6_IO1; additional SDADC3_AIN8P."+ },+ {+ "number": "35",+ "name": "PB15",+ "type": "bidirectional",+ "description": "Standard 3.3 V I/O (TC) powered by VDDSD3; alternate SPI2_MOSI/I2S2_SD, TIM15_CH1N, TIM15_CH2, TIM12_CH2, TSC_G6_IO2, RTC_REFIN; additional SDADC3_AIN7P and SDADC3_AIN8M."+ },+ {+ "number": "36",+ "name": "PD8",+ "type": "bidirectional",+ "description": "Standard 3.3 V I/O (TC) powered by VDDSD3; alternate SPI2_SCK/I2S2_CK, USART3_TX, TSC_G6_IO3; additional SDADC3_AIN6P."+ },+ {+ "number": "37",+ "name": "PC6",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate TIM3_CH1 and SPI1_NSS/I2S1_WS."+ },+ {+ "number": "38",+ "name": "PC7",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate TIM3_CH2 and SPI1_SCK/I2S1_CK."+ },+ {+ "number": "39",+ "name": "PC8",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate SPI1_MISO/I2S1_MCK and TIM3_CH3."+ },+ {+ "number": "40",+ "name": "PC9",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate SPI1_MOSI/I2S1_SD and TIM3_CH4."+ },+ {+ "number": "41",+ "name": "PA8",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate MCO, SPI2_SCK/I2S2_CK, I2C2_SMBA, USART1_CK, TIM4_ETR, TIM5_CH1_ETR."+ },+ {+ "number": "42",+ "name": "PA9",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); alternate I2C2_SCL, USART1_TX, SPI2_MISO/I2S2_MCK, TIM2_CH3, TIM15_BKIN, TIM13_CH1, TSC_G4_IO1."+ },+ {+ "number": "43",+ "name": "PA10",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); alternate I2C2_SDA, USART1_RX, SPI2_MOSI/I2S2_SD, TIM2_CH4, TIM17_BKIN, TIM14_CH1, TSC_G4_IO2."+ },+ {+ "number": "44",+ "name": "PA11",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate CAN_RX, USB_DM, USART1_CTS, SPI2_NSS/I2S2_WS, SPI1_NSS/I2S1_WS, TIM4_CH1, TIM5_CH2, COMP1_OUT."+ },+ {+ "number": "45",+ "name": "PA12",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate CAN_TX, USB_DP, USART1_RTS, SPI1_SCK/I2S1_CK, TIM16_CH1, TIM4_CH2, TIM5_CH3, COMP2_OUT."+ },+ {+ "number": "46",+ "name": "PA13",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); default debug function SWDIO-JTMS, alternate IR_OUT, USART3_CTS, SPI1_MISO/I2S1_MCK, TIM16_CH1N, TIM4_CH3, TIM5_CH4, TSC_G4_IO3."+ },+ {+ "number": "47",+ "name": "PF6",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); alternate I2C2_SCL, SPI1_MOSI/I2S1_SD, USART3_RTS, TIM4_CH4."+ },+ {+ "number": "48",+ "name": "PF7",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); alternate I2C2_SDA and USART2_CK."+ },+ {+ "number": "49",+ "name": "PA14",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); default debug function SWCLK-JTCK, alternate I2C1_SDA, TIM12_CH1, TSC_G4_IO4."+ },+ {+ "number": "50",+ "name": "PA15",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); default debug function JTDI, alternate I2C1_SCL, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, TIM2_CH1_ETR, TIM12_CH2, TSC_SYNC."+ },+ {+ "number": "51",+ "name": "PC10",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate SPI3_SCK/I2S3_CK, USART3_TX, TIM19_CH1."+ },+ {+ "number": "52",+ "name": "PC11",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate SPI3_MISO/I2S3_MCK, USART3_RX, TIM19_CH2."+ },+ {+ "number": "53",+ "name": "PC12",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate SPI3_MOSI/I2S3_SD, USART3_CK, TIM19_CH3."+ },+ {+ "number": "54",+ "name": "PD2",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate TIM3_ETR."+ },+ {+ "number": "55",+ "name": "PB3",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); default debug function JTDO-TRACESWO, alternate SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, USART2_TX, TIM2_CH2, TIM3_ETR, TIM4_ETR, TIM13_CH1, TSC_G5_IO1."+ },+ {+ "number": "56",+ "name": "PB4",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); default function NJTRST, alternate SPI1_MISO/I2S1_MCK, SPI3_MISO/I2S3_MCK, USART2_RX, TIM16_CH1, TIM3_CH1, TIM17_BKIN, TIM15_CH1N, TSC_G5_IO2."+ },+ {+ "number": "57",+ "name": "PB5",+ "type": "bidirectional",+ "description": "5 V tolerant I/O (FT); alternate I2C1_SMBA, SPI1_MOSI/I2S1_SD, SPI3_MOSI/I2S3_SD, USART2_CK, TIM16_BKIN, TIM3_CH2, TIM17_CH1, TIM19_ETR."+ },+ {+ "number": "58",+ "name": "PB6",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); alternate I2C1_SCL, USART1_TX, TIM16_CH1N, TIM3_CH3, TIM4_CH1, TIM19_CH1, TIM15_CH1, TSC_G5_IO3."+ },+ {+ "number": "59",+ "name": "PB7",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); alternate I2C1_SDA, USART1_RX, TIM17_CH1N, TIM3_CH4, TIM4_CH2, TIM19_CH2, TIM15_CH2, TSC_G5_IO4."+ },+ {+ "number": "60",+ "name": "BOOT0",+ "type": "input",+ "description": "Dedicated BOOT0 input pin used for boot memory selection."+ },+ {+ "number": "61",+ "name": "PB8",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); alternate I2C1_SCL, SPI2_SCK/I2S2_CK, CEC, USART3_TX, CAN_RX, TIM16_CH1, TIM4_CH3, TIM19_CH3, COMP1_OUT, TSC_SYNC."+ },+ {+ "number": "62",+ "name": "PB9",+ "type": "bidirectional",+ "description": "5 V tolerant I/O with FM+ capability (FTf); alternate I2C1_SDA, SPI2_NSS/I2S2_WS, IR_OUT, USART3_RX, CAN_TX, TIM17_CH1, TIM4_CH4, TIM19_CH4, COMP2_OUT."+ },+ {+ "number": "63",+ "name": "VSS_1",+ "type": "power_in",+ "description": "Digital ground."+ },+ {+ "number": "64",+ "name": "VDD_1",+ "type": "power_in",+ "description": "Digital power supply; the device operating voltage range is 2.0 to 3.6 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Package confirmed as LQFP64 (10 x 10 mm): the ordering scheme in Table 82 gives R = 64 pins and T = ; Pin 17 is VREF+ and pin 1 is VBAT in the LQFP64 column; the source table rows for these are out of s; Pins 31 and 32 have combined names in the datasheet (VSSSD/VREFSD- and VDDSD) and are shared with th"+ ],+ "pages_sent": 57,+ "cost_usd": 0.2879,+ "at": "2026-10-07T23:16:56"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586176370364203008",+ "pages": 137,+ "sha256": "fd00ebf096b21764",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "stm32f373rct6.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b0c827bc5c05552175d28affe44a5bd2ab45c9c36efff6ff07a74cc449b13db4",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "stm32f373rct6-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "69a9d6807fb44d75b4715d7074194b05b7a2c1d959627224e4cb79cbe1b64105",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}