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STL60N32N3LL-VB
Public Made by Adomby adom
VBsemi Elec MOSFETs, DFN5x6-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+123−8@@ -1,13 +1,133 @@ {+ "schema_version": 1,+ "type": "component", "slug": "stl60n32n3ll-vb",+ "title": "STL60N32N3LL-VB",+ "brief": "VBsemi Elec MOSFETs, DFN5x6-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "VBsemi Elec MOSFETs, DFN5x6-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "transistors-thyristors", "stl60n32n3ll-vb" ],+ "component": {+ "mpn": "STL60N32N3LL-VB",+ "manufacturer": "VBsemi Elec",+ "package": "DFN5x6-8",+ "pin_count": 9,+ "category": "Transistors/Thyristors",+ "subcategory": "MOSFETs",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604413219969134592",+ "parts": {+ "symbol": "stl60n32n3ll-vb.kicad_sym",+ "footprint": "stl60n32n3ll-vb.kicad_mod",+ "model_3d": "stl60n32n3ll-vb.glb",+ "model_3d_step": "stl60n32n3ll-vb.step",+ "lbr": "stl60n32n3ll-vb.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "G1",+ "type": "input",+ "description": "Gate of MOSFET Q1 (high-side FET in the half-bridge). VGS(th) typ 1.0-2.5 V, VGS abs max \u00b120 V. Drives the top FET whose source is the PHASE (S1/D2) node."+ },+ {+ "number": "2",+ "name": "D1",+ "type": "passive",+ "description": "Drain of MOSFET Q1 (high-side). Pins 2, 3 and 4 are ganged together as the D1 lead. Typically tied to the input supply rail (VIN) in a synchronous-buck power stage."+ },+ {+ "number": "3",+ "name": "D1",+ "type": "passive",+ "description": "Drain of MOSFET Q1 (high-side), ganged with pins 2 and 4. Multiple pins are provided to reduce lead resistance/inductance and to spread current/heat."+ },+ {+ "number": "4",+ "name": "D1",+ "type": "passive",+ "description": "Drain of MOSFET Q1 (high-side), ganged with pins 2 and 3."+ },+ {+ "number": "5",+ "name": "S2",+ "type": "passive",+ "description": "Source of MOSFET Q2 (low-side FET in the half-bridge). Pins 5, 6 and 7 are ganged together as the S2 lead. Typically tied to PGND in a synchronous-buck power stage."+ },+ {+ "number": "6",+ "name": "S2",+ "type": "passive",+ "description": "Source of MOSFET Q2 (low-side), ganged with pins 5 and 7. Multiple pins reduce lead resistance/inductance."+ },+ {+ "number": "7",+ "name": "S2",+ "type": "passive",+ "description": "Source of MOSFET Q2 (low-side), ganged with pins 5 and 6."+ },+ {+ "number": "8",+ "name": "G2",+ "type": "input",+ "description": "Gate of MOSFET Q2 (low-side FET in the half-bridge). VGS(th) typ 1.0-2.5 V, VGS abs max \u00b120 V."+ },+ {+ "number": "9",+ "name": "S1/D2",+ "type": "passive",+ "description": "Exposed thermal/electrical pad - internally tied source of Q1 to drain of Q2, forming the switch (PHASE / SW / LX) node of the half-bridge. Carries the full switched load current; must be soldered to a large copper area both for the electrical connection and for heat sinking."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8604413219969134592",+ "pages": null,+ "sha256": "9ccdbe6791781a25",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 9,+ "described": 9,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "VBsemi Elec",+ "Package": "DFN5x6-8",+ "Category": "Transistors/Thyristors",+ "Pins": "9"+ }+ },+ "variants": [],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "stl60n32n3ll-vb"+ ],+ "discovery_pitch": "STL60N32N3LL-VB (VBsemi Elec) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +145,5 @@ "docs/stl60n32n3ll-vb-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }