component
STD5NK40ZT4
Public Made by Adomby adom
STMicroelectronics MOSFETs, DPAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+39@@ -0,0 +1,39 @@+# STD5NK40ZT4++**STMicroelectronics** · MOSFETs · DPAK++STD5NK40ZT4 from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Gate | input | Gate terminal for MOSFET switching control with maximum gate-source voltage ±30V and integrated Zener diode protection. |+| 2 | Drain | passive | Drain terminal rated for maximum 400V drain-source voltage; connected to case tab for thermal dissipation path. |+| 3 | Source | power_in | Source terminal providing reference potential for gate and drain voltages; typical return path connection. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | DPAK |+| Category | Transistors/Thyristors |+| Pins | 3 |++## CAD (KiCad official)++- Symbol: `STD5NK40ZT4`+- Footprint: `Package_TO_SOT_SMD:TO-252-2`+- 3D model: DPAK (KiCad packages3D, STEP)+- 3D model files: `std5nk40zt4-etched.step` / `std5nk40zt4-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `std5nk40zt4.step` / `std5nk40zt4.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885409350209536) (13 pp, sha256 `471b445d2f8e7e19`, retrieved 2026-10-01, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/std5nk40zt4-datasheet.pdf)
page.jsonadded+128@@ -0,0 +1,128 @@+{+ "slug": "std5nk40zt4",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics MOSFETs, DPAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "transistors-thyristors",+ "std5nk40zt4",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "std5nk40zt4.kicad_sym",+ "std5nk40zt4.kicad_mod",+ "std5nk40zt4.glb",+ "std5nk40zt4.step",+ "std5nk40zt4.lbr",+ "docs/hero.png",+ "docs/std5nk40zt4-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "STD5NK40ZT4",+ "manufacturer": "STMicroelectronics",+ "package": "DPAK",+ "pin_count": 3,+ "category": "Transistors/Thyristors",+ "subcategory": "MOSFETs",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885409350209536",+ "parts": {+ "symbol": "std5nk40zt4.kicad_sym",+ "footprint": "std5nk40zt4.kicad_mod",+ "model_3d": "std5nk40zt4-etched.glb",+ "model_3d_plain": "std5nk40zt4.glb",+ "model_3d_step": "std5nk40zt4-etched.step",+ "model_3d_step_plain": "std5nk40zt4.step",+ "lbr": "std5nk40zt4.lbr"+ },+ "distributor_links": {+ "lcsc": "C262933",+ "digikey": "497-2477-2-ND",+ "mouser": "511-STD5NK40Z"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T00:20:50Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-2477-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-STD5NK40Z",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "Gate",+ "type": "input",+ "description": "Gate terminal for MOSFET switching control with maximum gate-source voltage ±30V and integrated Zener diode protection."+ },+ {+ "number": "2",+ "name": "Drain",+ "type": "passive",+ "description": "Drain terminal rated for maximum 400V drain-source voltage; connected to case tab for thermal dissipation path."+ },+ {+ "number": "3",+ "name": "Source",+ "type": "power_in",+ "description": "Source terminal providing reference potential for gate and drain voltages; typical return path connection."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Explicit pin function descriptions are not provided in datasheet text. Pin function assignments (Gat"+ ],+ "pages_sent": 13,+ "cost_usd": 0.1561,+ "at": "2026-10-01T00:20:36"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885409350209536",+ "pages": 13,+ "sha256": "471b445d2f8e7e19",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 3,+ "described": 3,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}