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Initial commit: component/std100n3lf3

Ray ·66bff22556 ·10h ago
2 files changed +211
README.mdadded+39
@@ -0,0 +1,39 @@+# STD100N3LF3++**STMicroelectronics** · MOSFETs · DPAK++STD100N3LF3 from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | G | input | Gate; gate-source voltage limited to ±20 V with a gate threshold of 1 V min to 2.5 V max at ID = 250 µA. |+| 2 | D | passive | Drain (also the TAB); drain-source voltage 30 V max and 80 A continuous drain current at TC = 25 °C, limited by package. |+| 3 | S | passive | Source; source-drain diode current 80 A continuous and 320 A pulsed. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | DPAK |+| Category | Transistors/Thyristors |+| Pins | 3 |++## CAD (KiCad official)++- Symbol: `STD100N3LF3`+- Footprint: `Package_TO_SOT_SMD:TO-252-2`+- 3D model: DPAK (KiCad packages3D, STEP)+- 3D model files: `std100n3lf3-etched.step` / `std100n3lf3-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `std100n3lf3.step` / `std100n3lf3.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603061198522753024) (14 pp, sha256 `aad9c77e7a6d0140`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/std100n3lf3-datasheet.pdf)
page.jsonadded+172
@@ -0,0 +1,172 @@+{+  "slug": "std100n3lf3",+  "version": "0.1.0",+  "type": "component",+  "description": "STMicroelectronics MOSFETs, DPAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "transistors-thyristors",+    "std100n3lf3",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "std100n3lf3.kicad_sym",+    "std100n3lf3.kicad_mod",+    "std100n3lf3.glb",+    "std100n3lf3.step",+    "std100n3lf3.lbr",+    "docs/hero.png",+    "docs/std100n3lf3-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "std100n3lf3-hero.glb",+    "std100n3lf3-hero.overlay.json"+  ],+  "component": {+    "mpn": "STD100N3LF3",+    "manufacturer": "STMicroelectronics",+    "package": "DPAK",+    "pin_count": 3,+    "category": "Transistors/Thyristors",+    "subcategory": "MOSFETs",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603061198522753024",+    "parts": {+      "symbol": "std100n3lf3.kicad_sym",+      "footprint": "std100n3lf3.kicad_mod",+      "model_3d": "std100n3lf3-hero.glb",+      "model_3d_plain": "std100n3lf3.glb",+      "model_3d_step": "std100n3lf3-etched.step",+      "model_3d_step_plain": "std100n3lf3.step",+      "lbr": "std100n3lf3.lbr"+    },+    "distributor_links": {+      "lcsc": "C2970469",+      "digikey": "497-16197-2-ND",+      "mouser": "511-STD100N3LF3"+    },+    "distributor_check": {+      "checked_at": "2026-10-07T08:16:35Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "497-16197-2-ND",+        "status": "found",+        "lifecycle": "Obsolete"+      },+      "mouser": {+        "pn": "511-STD100N3LF3",+        "status": "found",+        "lifecycle": "Obsolete"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "G",+        "type": "input",+        "description": "Gate; gate-source voltage limited to ±20 V with a gate threshold of 1 V min to 2.5 V max at ID = 250 µA."+      },+      {+        "number": "2",+        "name": "D",+        "type": "passive",+        "description": "Drain (also the TAB); drain-source voltage 30 V max and 80 A continuous drain current at TC = 25 °C, limited by package."+      },+      {+        "number": "3",+        "name": "S",+        "type": "passive",+        "description": "Source; source-drain diode current 80 A continuous and 320 A pulsed."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-sonnet-5-5",+        "primary_mode": "text+vision",+        "consensus_model": "claude-opus-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: The drain tab is the same net as pin 2. Figure 1 labels it 'D (TAB or 2)', so the tab is not listed ",+          "vision extraction: provenance cannot be text-verified; needs consensus"+        ],+        "pages_sent": 14,+        "cost_usd": 0.1548,+        "at": "2026-10-07T08:16:22"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603061198522753024",+        "pages": 14,+        "sha256": "aad9c77e7a6d0140",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 3,+        "described": 3,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "std100n3lf3.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          9.9,+          6.5,+          2.32+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "3eb4c99603a4fe837c2fe9308bc174769ded87a785a0df48d2dc441432ee8b4c",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "std100n3lf3-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          9.9,+          6.5,+          2.32+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "546ee6549b53d5b4b37bff7712a028424e08ba7bc8769d7366f02b54a69c169f",+        "checked": "2026-10-07",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file