STC15F2K60S2-28I-LQFP44

@@ -0,0 +1,91 @@+# STC15F2K60S2-28I-LQFP44++**STC Micro** · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)++STC15F2K60S2-28I-LQFP44 from STC Micro, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | P0.5/AD5 | bidirectional | Port 0 bit 5, quasi-bidirectional I/O (weak pull-up after reset). Multiplexed as multiplexed address/data bus bit AD5 when external memory bus is used. |+| 2 | P0.6/AD6 | bidirectional | Port 0 bit 6, quasi-bidirectional I/O. Multiplexed address/data bus bit AD6. |+| 3 | P0.7/AD7 | bidirectional | Port 0 bit 7, quasi-bidirectional I/O. Multiplexed address/data bus bit AD7. |+| 4 | P1.0/ADC0/CCP1/RxD2 | bidirectional | Port 1 bit 0. Alternate functions: ADC channel 0 input; CCP/PCA channel 1 capture/compare/PWM I/O; UART2 receive. |+| 5 | P1.1/ADC1/CCP0/TxD2 | bidirectional | Port 1 bit 1. Alternate functions: ADC channel 1 input; CCP/PCA channel 0; UART2 transmit. |+| 6 | P4.7/TxD2_2 | bidirectional | Port 4 bit 7, quasi-bidirectional I/O. Alternate function: UART2 alternate transmit output (TxD2_2). |+| 7 | P1.2/ADC2/SS/ECI | bidirectional | Port 1 bit 2. Alternate: ADC ch2, SPI slave-select (SS), PCA external clock input (ECI). |+| 8 | P1.3/ADC3/MOSI | bidirectional | Port 1 bit 3. Alternate: ADC ch3; SPI MOSI (master-out/slave-in). |+| 9 | P1.4/ADC4/MISO | bidirectional | Port 1 bit 4. Alternate: ADC ch4; SPI MISO. |+| 10 | P1.5/ADC5/SCLK | bidirectional | Port 1 bit 5. Alternate: ADC ch5; SPI SCLK. |+| 11 | P1.6/ADC6/RxD_3/XTAL2 | bidirectional | Port 1 bit 6. Alternate: ADC ch6; UART1 alternate receive (RxD_3); crystal oscillator output XTAL2 (leave floating when using external clock). |+| 12 | P1.7/ADC7/TxD_3/XTAL1 | bidirectional | Port 1 bit 7. Alternate: ADC ch7; UART1 alternate transmit (TxD_3); crystal oscillator input XTAL1 (or external clock input). |+| 13 | P5.4/RST/MCLKO/SS_3 | bidirectional | Port 5 bit 4. Alternate: active-high hardware reset input RST (when enabled by config); master clock output MCLKO (MCLK/1, /2 or /4); SPI alternate slave-select SS_3. |+| 14 | Vcc | power_in | Positive supply. STC15F2K60S2 accepts 5.5 V to 3.8 V; the -L variant (STC15L2K60S2) covers 3.6 V to 2.4 V. |+| 15 | P5.5 | bidirectional | Port 5 bit 5, general-purpose quasi-bidirectional I/O. |+| 16 | Gnd | power_in | Ground (0 V) reference for the supply. |+| 17 | P4.0/MOSI_3 | bidirectional | Port 4 bit 0. Alternate: SPI alternate MOSI (MOSI_3). |+| 18 | P3.0/RxD/INT4/T2CLKO | bidirectional | Port 3 bit 0. Alternate: UART1 receive (RxD); external interrupt 4 (falling-edge only, supports power-down wake-up); Timer/Counter 2 clock output. |+| 19 | P3.1/TxD/T2 | bidirectional | Port 3 bit 1. Alternate: UART1 transmit (TxD); Timer/Counter 2 external input. |+| 20 | P3.2/INT0 | bidirectional | Port 3 bit 2. Alternate: external interrupt 0 (rising and/or falling edge per IT0; supports power-down wake-up). |+| 21 | P3.3/INT1 | bidirectional | Port 3 bit 3. Alternate: external interrupt 1 (rising and/or falling edge per IT1; supports power-down wake-up). |+| 22 | P3.4/T0/T1CLKO/ECI_2 | bidirectional | Port 3 bit 4. Alternate: Timer/Counter 0 external input; Timer 1 programmable clock output (T1CLKO); PCA external clock input alternate (ECI_2). |+| 23 | P3.5/T1/T0CLKO/CCP0_2 | bidirectional | Port 3 bit 5. Alternate: Timer/Counter 1 external input; Timer 0 clock output (T0CLKO); CCP/PCA channel 0 alternate (CCP0_2). |+| 24 | P3.6/INT2/RxD_2/CCP1_2 | bidirectional | Port 3 bit 6. Alternate: external interrupt 2 (falling-edge only, wake-up capable); UART1 alternate receive (RxD_2); CCP/PCA channel 1 alternate. |+| 25 | P3.7/INT3/TxD_2/CCP2/CCP2_2 | bidirectional | Port 3 bit 7. Alternate: external interrupt 3 (falling-edge only, wake-up capable); UART1 alternate transmit (TxD_2); CCP/PCA channel 2 (primary and alternate mapping). |+| 26 | P4.1/MISO_3 | bidirectional | Port 4 bit 1. Alternate: SPI alternate MISO (MISO_3). |+| 27 | P4.2/WR | bidirectional | Port 4 bit 2. Alternate: external data-memory write strobe (/WR) for MOVX bus access. |+| 28 | P4.3/SCLK_3 | bidirectional | Port 4 bit 3. Alternate: SPI alternate clock (SCLK_3). |+| 29 | P4.4/RD | bidirectional | Port 4 bit 4. Alternate: external data-memory read strobe (/RD) for MOVX bus access. |+| 30 | P2.0/A8/RSTOUT_LOW | bidirectional | Port 2 bit 0. Alternate: address bus bit A8; RSTOUT_LOW - held low during and after reset (software may release). |+| 31 | P2.1/A9/SCLK_2 | bidirectional | Port 2 bit 1. Alternate: address bus bit A9; SPI alternate clock (SCLK_2). |+| 32 | P2.2/A10/MISO_2 | bidirectional | Port 2 bit 2. Alternate: address bus bit A10; SPI alternate MISO (MISO_2). |+| 33 | P2.3/A11/MOSI_2 | bidirectional | Port 2 bit 3. Alternate: address bus bit A11; SPI alternate MOSI (MOSI_2). |+| 34 | P2.4/A12/ECI_3/SS_2 | bidirectional | Port 2 bit 4. Alternate: address bus bit A12; PCA external clock input (ECI_3); SPI alternate slave-select (SS_2). |+| 35 | P2.5/A13/CCP0_3 | bidirectional | Port 2 bit 5. Alternate: address bus bit A13; CCP/PCA channel 0 alternate (CCP0_3). |+| 36 | P2.6/A14/CCP1_3 | bidirectional | Port 2 bit 6. Alternate: address bus bit A14; CCP/PCA channel 1 alternate (CCP1_3). |+| 37 | P2.7/A15/CCP2_3 | bidirectional | Port 2 bit 7. Alternate: address bus bit A15; CCP/PCA channel 2 alternate (CCP2_3). |+| 38 | P4.5/ALE | bidirectional | Port 4 bit 5. Alternate: address-latch-enable strobe (ALE) for external multiplexed address/data bus. |+| 39 | P4.6/RxD2_2 | bidirectional | Port 4 bit 6. Alternate: UART2 alternate receive (RxD2_2). |+| 40 | P0.0/AD0 | bidirectional | Port 0 bit 0, quasi-bidirectional I/O. Multiplexed address/data bus bit AD0. |+| 41 | P0.1/AD1 | bidirectional | Port 0 bit 1, quasi-bidirectional I/O. Multiplexed address/data bus bit AD1. |+| 42 | P0.2/AD2 | bidirectional | Port 0 bit 2, quasi-bidirectional I/O. Multiplexed address/data bus bit AD2. |+| 43 | P0.3/AD3 | bidirectional | Port 0 bit 3, quasi-bidirectional I/O. Multiplexed address/data bus bit AD3. |+| 44 | P0.4/AD4 | bidirectional | Port 0 bit 4, quasi-bidirectional I/O. Multiplexed address/data bus bit AD4. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STC Micro |+| Package | LQFP-44(10x10) |+| Category | MCU |+| Pins | 44 |++## Ordering variants++- `STC15F2K60S2-28I-LQFP44`+- `STC15F2K60S2-28I-LQFP4428I-PLCC44`+- `STC15F2K60S2-28I-LQFP4428I-PDIP40`+- `STC15F2K60S2-28I-LQFP4428I-LQFP32`+- `STC15F2K60S2-28I-LQFP4428I-SOP28`+- `STC15F2K60S2-28I-LQFP4428I-SKDIP28`+- `STC15F2K60S2-28I-LQFP4428I-SOP32`+- `STC15F2K60S2-28I-LQFP4428I-TSSOP20`++## CAD (KiCad official)++- Symbol: `STC15F2K60S2-28I-LQFP44`+- Footprint: `Package_QFP:LQFP-44_10x10mm_P0.8mm`+- 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STC Micro datasheet](docs/stc15f2k60s2-28i-lqfp44-datasheet.pdf) (1163 pp, sha256 `e51f2a7c23577f5f`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stc15f2k60s2-28i-lqfp44-datasheet.pdf)