STC12C5A60S2-35I-LQFP44

@@ -0,0 +1,87 @@+# STC12C5A60S2-35I-LQFP44++**STC Micro** · Microcontrollers (MCU/MPU/SOC) · LQFP-44(10x10)++STC12C5A60S2-35I-LQFP44 from STC Micro, in a LQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | P1.5/MOSI/ADC5 | bidirectional | Port 1 bit 5, quasi-bidirectional GPIO after reset. Alternate: SPI MOSI (master-out/slave-in), ADC channel 5 (10-bit, 0-VCC). Drive up to 20 mA per pin. |+| 2 | P1.6/MISO/ADC6 | bidirectional | Port 1 bit 6, quasi-bidirectional GPIO after reset. Alternate: SPI MISO, ADC channel 6. |+| 3 | P1.7/SCLK/ADC7 | bidirectional | Port 1 bit 7, quasi-bidirectional GPIO after reset. Alternate: SPI SCLK, ADC channel 7. |+| 4 | P4.7/RST | input | Default: active-high external reset input (RST). Can be programmed as P4.7 quasi-bidirectional GPIO via ISP option. Built-in MAX810 reset circuit is available. |+| 5 | P3.0/RxD | bidirectional | Port 3 bit 0. UART0 receive data (RxD) and also used by the ISP serial-download bootloader. |+| 6 | P4.3/SCLK/TxD2/CCP1 | bidirectional | Port 4 bit 3, quasi-bidirectional GPIO. Alternate: alternate SPI SCLK location, UART2 TxD alternate location, PCA/CCP1 alternate capture/compare pin. |+| 7 | P3.1/TxD | bidirectional | Port 3 bit 1. UART0 transmit data (TxD) and used by the ISP serial-download bootloader. |+| 8 | P3.2/INT0 | bidirectional | Port 3 bit 2. Alternate: external interrupt 0 (INT0), can wake MCU from power-down. |+| 9 | P3.3/INT1 | bidirectional | Port 3 bit 3. Alternate: external interrupt 1 (INT1), can wake MCU from power-down. |+| 10 | P3.4/T0/CLKOUT0 | bidirectional | Port 3 bit 4. Alternate: Timer 0 external input (T0), programmable clock output CLKOUT0 (T0 overflow). |+| 11 | P3.5/T1/CLKOUT1 | bidirectional | Port 3 bit 5. Alternate: Timer 1 external input (T1), programmable clock output CLKOUT1 (T1 overflow). |+| 12 | P3.6/WR | bidirectional | Port 3 bit 6. Alternate: external data memory write strobe (WR) when external bus is used. |+| 13 | P3.7/RD | bidirectional | Port 3 bit 7. Alternate: external data memory read strobe (RD) when external bus is used. |+| 14 | XTAL2 | output | Crystal oscillator output (drives external crystal from internal inverter). Leave open if using internal RC oscillator. |+| 15 | XTAL1 | input | Crystal oscillator input (or external clock input). Typical loading caps 15-47 pF. Drive with external clock or leave open if using internal RC oscillator. |+| 16 | GND | power_in | Ground / VSS. Common return for digital and analog supplies. |+| 17 | P4.0/SS | bidirectional | Port 4 bit 0. Alternate: SPI slave select (SS) alternate location. |+| 18 | P2.0 | bidirectional | Port 2 bit 0, quasi-bidirectional GPIO (also A8 of external address bus when external memory is used). |+| 19 | P2.1 | bidirectional | Port 2 bit 1, quasi-bidirectional GPIO (also A9 of external address bus). |+| 20 | P2.2 | bidirectional | Port 2 bit 2, quasi-bidirectional GPIO (also A10 of external address bus). |+| 21 | P2.3 | bidirectional | Port 2 bit 3, quasi-bidirectional GPIO (also A11 of external address bus). |+| 22 | P2.4 | bidirectional | Port 2 bit 4, quasi-bidirectional GPIO (also A12 of external address bus). |+| 23 | P2.5 | bidirectional | Port 2 bit 5, quasi-bidirectional GPIO (also A13 of external address bus). |+| 24 | P2.6 | bidirectional | Port 2 bit 6, quasi-bidirectional GPIO (also A14 of external address bus). |+| 25 | P2.7 | bidirectional | Port 2 bit 7, quasi-bidirectional GPIO (also A15 of external address bus). |+| 26 | P0.7 | bidirectional | Port 0 bit 7, quasi-bidirectional GPIO (also AD7 of external multiplexed address/data bus). |+| 27 | P0.6 | bidirectional | Port 0 bit 6, quasi-bidirectional GPIO (also AD6). |+| 28 | P0.5 | bidirectional | Port 0 bit 5, quasi-bidirectional GPIO (also AD5). |+| 29 | P0.4 | bidirectional | Port 0 bit 4, quasi-bidirectional GPIO (also AD4). |+| 30 | P4.4 | bidirectional | Port 4 bit 4, quasi-bidirectional GPIO. Marked NA (no alternate function) in this variant. |+| 31 | P4.5/ALE | bidirectional | Port 4 bit 5. Alternate: ALE (address-latch-enable) for external memory bus. |+| 32 | P4.1/ECI/MOSI | bidirectional | Port 4 bit 1. Alternate: PCA external clock input (ECI), SPI MOSI alternate location. |+| 33 | P4.6/EX_LVD/RST2 | bidirectional | Port 4 bit 6. Alternate: external low-voltage-detect comparator input EX_LVD (threshold ~1.32 V on 5 V parts, ~1.30 V on 3.3 V parts), and second reset input (RST2) with programmable threshold. |+| 34 | P0.3 | bidirectional | Port 0 bit 3, quasi-bidirectional GPIO (also AD3). |+| 35 | P0.2 | bidirectional | Port 0 bit 2, quasi-bidirectional GPIO (also AD2). |+| 36 | P0.1 | bidirectional | Port 0 bit 1, quasi-bidirectional GPIO (also AD1). |+| 37 | P0.0 | bidirectional | Port 0 bit 0, quasi-bidirectional GPIO (also AD0). |+| 38 | VCC | power_in | Digital supply. 3.3-5.5 V for STC12C5A60S2 (5 V parts); 2.2-3.6 V for STC12LE5A60S2 (3.3 V parts). Decouple with 10 uF bulk + 0.1 uF to GND close to the pin. |+| 39 | P4.2/MISO/RxD2/CCP0 | bidirectional | Port 4 bit 2. Alternate: SPI MISO alternate location, UART2 RxD alternate location, PCA/CCP0 alternate capture/compare pin. |+| 40 | P1.0/ADC0/CLKOUT2 | bidirectional | Port 1 bit 0. Alternate: ADC channel 0 (10-bit), programmable clock output CLKOUT2 (baud-rate-generator overflow). |+| 41 | P1.1/ADC1 | bidirectional | Port 1 bit 1. Alternate: ADC channel 1. |+| 42 | P1.2/RxD2/ECI/ADC2 | bidirectional | Port 1 bit 2. Alternate: UART2 RxD (default location), PCA external clock input (ECI), ADC channel 2. |+| 43 | P1.3/TxD2/CCP0/ADC3 | bidirectional | Port 1 bit 3. Alternate: UART2 TxD (default location), PCA/CCP0 (default location), ADC channel 3. |+| 44 | P1.4/SS/CCP1/ADC4 | bidirectional | Port 1 bit 4. Alternate: SPI slave select (SS, default), PCA/CCP1 (default location), ADC channel 4. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STC Micro |+| Package | LQFP-44(10x10) |+| Category | MCU |+| Pins | 44 |++## Ordering variants++- `STC12C5A60S2-35I-LQFP44LQFP44`+- `STC12C5A60S2-35I-LQFP44PDIP40`+- `STC12C5A60S2-35I-LQFP44LQFP48`+- `STC12C5A60S2-35I-LQFP44PLCC44`++## CAD (KiCad official)++- Symbol: `STC12C5A60S2-35I-LQFP44`+- Footprint: `Package_QFP:LQFP-44_10x10mm_P0.8mm`+- 3D model: LQFP-44(10x10) (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STC Micro datasheet](docs/stc12c5a60s2-35i-lqfp44-datasheet.pdf) (1543 pp, sha256 `7fde44da8887b7a0`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stc12c5a60s2-35i-lqfp44-datasheet.pdf)