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Initial commit: component/stb55nf06t4

Ray ·37444c9175 ·9d ago
2 files changed +165
README.mdadded+39
@@ -0,0 +1,39 @@+# STB55NF06T4++**STMicroelectronics** · MOSFETs · D2PAK++STB55NF06T4 from STMicroelectronics, in a D2PAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Gate | input | Gate control terminal; accepts gate-source voltage from -20 V to +20 V (VGS max ±20 V) to modulate drain current conduction. |+| 2 | Drain | output | Drain terminal; rated for 60 V maximum drain-source voltage (VDS) and 50 A continuous drain current at TC = 25°C; typical on-state resistance (RDS(on)) 0.015 Ω. |+| 3 | Source | power_in | Source terminal; provides return current path for drain and serves as reference point for gate-source voltage (VGS ±20 V maximum relative to this pin). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | D2PAK |+| Category | Transistors/Thyristors |+| Pins | 3 |++## CAD (KiCad official)++- Symbol: `STB55NF06T4`+- Footprint: `Package_TO_SOT_SMD:TO-263-2`+- 3D model: D2PAK (KiCad packages3D, STEP)+- 3D model files: `stb55nf06t4-etched.step` / `stb55nf06t4-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `stb55nf06t4.step` / `stb55nf06t4.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885417018208256) (19 pp, sha256 `f299654214e0dc37`, retrieved 2026-09-26, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/stb55nf06t4-datasheet.pdf)
page.jsonadded+126
@@ -0,0 +1,126 @@+{+  "slug": "stb55nf06t4",+  "version": "0.1.0",+  "type": "component",+  "description": "STMicroelectronics MOSFETs, D2PAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "transistors-thyristors",+    "stb55nf06t4",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "stb55nf06t4.kicad_sym",+    "stb55nf06t4.kicad_mod",+    "stb55nf06t4.glb",+    "stb55nf06t4.step",+    "stb55nf06t4.lbr",+    "docs/hero.png",+    "docs/stb55nf06t4-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "STB55NF06T4",+    "manufacturer": "STMicroelectronics",+    "package": "D2PAK",+    "pin_count": 3,+    "category": "Transistors/Thyristors",+    "subcategory": "MOSFETs",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885417018208256",+    "parts": {+      "symbol": "stb55nf06t4.kicad_sym",+      "footprint": "stb55nf06t4.kicad_mod",+      "model_3d": "stb55nf06t4-etched.glb",+      "model_3d_plain": "stb55nf06t4.glb",+      "model_3d_step": "stb55nf06t4-etched.step",+      "model_3d_step_plain": "stb55nf06t4.step",+      "lbr": "stb55nf06t4.lbr"+    },+    "distributor_links": {+      "lcsc": "C472532",+      "digikey": "497-6553-2-ND",+      "mouser": "511-STB55NF06"+    },+    "distributor_check": {+      "checked_at": "2026-09-26T17:26:04Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "497-6553-2-ND",+        "status": "found",+        "lifecycle": "Active"+      },+      "mouser": {+        "pn": "511-STB55NF06",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "Gate",+        "type": "input",+        "description": "Gate control terminal; accepts gate-source voltage from -20 V to +20 V (VGS max ±20 V) to modulate drain current conduction."+      },+      {+        "number": "2",+        "name": "Drain",+        "type": "output",+        "description": "Drain terminal; rated for 60 V maximum drain-source voltage (VDS) and 50 A continuous drain current at TC = 25°C; typical on-state resistance (RDS(on)) 0.015 Ω."+      },+      {+        "number": "3",+        "name": "Source",+        "type": "power_in",+        "description": "Source terminal; provides return current path for drain and serves as reference point for gate-source voltage (VGS ±20 V maximum relative to this pin)."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 19,+        "cost_usd": 0.1563,+        "at": "2026-09-26T17:25:49"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885417018208256",+        "pages": 19,+        "sha256": "f299654214e0dc37",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 3,+        "described": 3,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file