component
SQ4410EY-T1_GE3
Public Made by Adomby adom
Vishay Intertech MOSFETs, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+122−8@@ -1,13 +1,132 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sq4410ey-t1-ge3",+ "title": "SQ4410EY-T1_GE3",+ "brief": "Vishay Intertech MOSFETs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Vishay Intertech MOSFETs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "transistors-thyristors", "sq4410ey-t1_ge3" ],+ "component": {+ "mpn": "SQ4410EY-T1_GE3",+ "manufacturer": "Vishay Intertech",+ "package": "SOIC-8",+ "pin_count": 8,+ "category": "Transistors/Thyristors",+ "subcategory": "MOSFETs",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590400060950142976",+ "parts": {+ "symbol": "sq4410ey-t1-ge3.kicad_sym",+ "footprint": "sq4410ey-t1-ge3.kicad_mod",+ "model_3d": "sq4410ey-t1-ge3.glb",+ "model_3d_step": "sq4410ey-t1-ge3.step",+ "lbr": "sq4410ey-t1-ge3.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "S",+ "type": "passive",+ "description": "Source terminal of the N-Channel MOSFET. Tied internally to pins 2 and 3 (all three source pins are ganged)."+ },+ {+ "number": "2",+ "name": "S",+ "type": "passive",+ "description": "Source terminal of the N-Channel MOSFET. Tied internally to pins 1 and 3."+ },+ {+ "number": "3",+ "name": "S",+ "type": "passive",+ "description": "Source terminal of the N-Channel MOSFET. Tied internally to pins 1 and 2."+ },+ {+ "number": "4",+ "name": "G",+ "type": "input",+ "description": "Gate terminal of the N-Channel MOSFET. VGS(th) = 1.5-2.5 V; absolute maximum VGS = \u00b120 V. Gate resistance ~0.5-2 \u03a9 at 1 MHz; total gate charge Qg ~35 nC at VGS = 10 V."+ },+ {+ "number": "5",+ "name": "D",+ "type": "passive",+ "description": "Drain terminal of the N-Channel MOSFET. Tied internally to pins 6, 7, and 8 (all four drain pins are ganged for improved current and thermal handling)."+ },+ {+ "number": "6",+ "name": "D",+ "type": "passive",+ "description": "Drain terminal of the N-Channel MOSFET. Tied internally to pins 5, 7, and 8."+ },+ {+ "number": "7",+ "name": "D",+ "type": "passive",+ "description": "Drain terminal of the N-Channel MOSFET. Tied internally to pins 5, 6, and 8. VDS max = 30 V."+ },+ {+ "number": "8",+ "name": "D",+ "type": "passive",+ "description": "Drain terminal of the N-Channel MOSFET. Tied internally to pins 5, 6, and 7. Primary thermal path (junction-to-foot RthJF = 30 \u00b0C/W)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590400060950142976",+ "pages": null,+ "sha256": "941cd7cbfcee6f6f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Vishay Intertech",+ "Package": "SOIC-8",+ "Category": "Transistors/Thyristors",+ "Pins": "8"+ }+ },+ "variants": [+ {+ "mpn": "SQ4410EY-T1_GE3",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sq4410ey-t1_ge3"+ ],+ "discovery_pitch": "SQ4410EY-T1_GE3 (Vishay Intertech) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +144,5 @@ "docs/sq4410ey-t1-ge3-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }