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Initial commit: component/sq4410ey-t1-ge3

Ray ·3ed06ae68f ·1mo ago
2 files changed +83
README.mdadded+49
@@ -0,0 +1,49 @@+# SQ4410EY-T1_GE3++**Vishay Intertech** · MOSFETs · SOIC-8++SQ4410EY-T1_GE3 from Vishay Intertech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | S | passive | Source terminal of the N-Channel MOSFET. Tied internally to pins 2 and 3 (all three source pins are ganged). |+| 2 | S | passive | Source terminal of the N-Channel MOSFET. Tied internally to pins 1 and 3. |+| 3 | S | passive | Source terminal of the N-Channel MOSFET. Tied internally to pins 1 and 2. |+| 4 | G | input | Gate terminal of the N-Channel MOSFET. VGS(th) = 1.5-2.5 V; absolute maximum VGS = ±20 V. Gate resistance ~0.5-2 Ω at 1 MHz; total gate charge Qg ~35 nC at VGS = 10 V. |+| 5 | D | passive | Drain terminal of the N-Channel MOSFET. Tied internally to pins 6, 7, and 8 (all four drain pins are ganged for improved current and thermal handling). |+| 6 | D | passive | Drain terminal of the N-Channel MOSFET. Tied internally to pins 5, 7, and 8. |+| 7 | D | passive | Drain terminal of the N-Channel MOSFET. Tied internally to pins 5, 6, and 8. VDS max = 30 V. |+| 8 | D | passive | Drain terminal of the N-Channel MOSFET. Tied internally to pins 5, 6, and 7. Primary thermal path (junction-to-foot RthJF = 30 °C/W). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Vishay Intertech |+| Package | SOIC-8 |+| Category | Transistors/Thyristors |+| Pins | 8 |++## Ordering variants++Same part, different packaging or reel option.++- `SQ4410EY-T1_GE3`++## CAD (KiCad official)++- Symbol: `SQ4410EY-T1_GE3`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Vishay Intertech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590400060950142976) (None pp, sha256 `941cd7cbfcee6f6f`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sq4410ey-t1-ge3-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "sq4410ey-t1-ge3",+  "version": "0.1.0",+  "type": "component",+  "description": "Vishay Intertech MOSFETs, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "transistors-thyristors",+    "sq4410ey-t1_ge3"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "sq4410ey-t1-ge3.kicad_sym",+    "sq4410ey-t1-ge3.kicad_mod",+    "sq4410ey-t1-ge3.glb",+    "sq4410ey-t1-ge3.step",+    "sq4410ey-t1-ge3.lbr",+    "docs/hero.png",+    "docs/sq4410ey-t1-ge3-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file