component
SPC560P40L1CEFBR
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+100@@ -0,0 +1,100 @@+# SPC560P40L1CEFBR++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)++SPC560P40L1CEFBR from STMicroelectronics, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | NMI | input | Non-maskable interrupt input only, on a slow pad. |+| 2 | A[6] | bidirectional | GPIO[6] (port A, slow/medium pad) with SCK of DSPI_1 and EIRQ[6] as alternate functions. |+| 3 | A[7] | bidirectional | GPIO[7] (port A, slow/medium pad) with SOUT of DSPI_1 and EIRQ[7] as alternate functions. |+| 4 | A[8] | bidirectional | GPIO[8] (port A, slow/medium pad) with SIN of DSPI_1 and EIRQ[8] as alternate functions. |+| 5 | A[5] | bidirectional | GPIO[5] (port A, slow/medium pad) with CS0 and CS7 chip-select functions and EIRQ[5] as alternate functions. |+| 6 | VDD_HV_IO1 | power_in | 3.3 V or 5.0 V input/output supply voltage; absolute maximum range is -0.3 V to 6.0 V. |+| 7 | VSS_HV_IO1 | power_in | Input/output ground for the VDD_HV_IO1 segment. |+| 8 | D[9] | bidirectional | GPIO[57] (port D, slow/medium pad) with X[0] of FlexPWM_0 and TXD of LIN_1 as alternate functions. |+| 9 | VDD_HV_OSC | power_in | 3.3 V or 5.0 V crystal oscillator amplifier supply voltage. |+| 10 | VSS_HV_OSC | power_in | Crystal oscillator amplifier ground. |+| 11 | XTAL | passive | Analog output of the oscillator amplifier circuit; it must be grounded if the oscillator is used in bypass mode. |+| 12 | EXTAL | input | Analog input of the oscillator amplifier circuit when not in bypass mode, and analog clock input when the oscillator is in bypass mode. |+| 13 | RESET | bidirectional | Bidirectional reset pin with Schmitt trigger characteristics and noise filter. |+| 14 | D[8] | bidirectional | GPIO[56] (port D, slow/medium pad) with CS2 and CS5 chip-select functions as alternate functions. |+| 15 | VSS_LV_COR0 | power_in | 1.2 V ground for core logic and PLL; the decoupling capacitor must be connected to the nearest VDD_LV_COR pin. |+| 16 | VDD_LV_COR0 | power_in | 1.2 V supply for core logic and PLL; the decoupling capacitor must be connected to the nearest VSS_LV_COR pin. |+| 17 | D[7] | bidirectional | GPIO[55] (port D, slow/medium pad) with CS3, CS4, and F[1] of FCU_0 as alternate functions. |+| 18 | E[1] | input | Input-only GPIO[65] pad that also serves as ADC_0 analog input AN[4]. |+| 19 | C[1] | input | Input-only GPIO[33] pad that also serves as ADC_0 analog input AN[2]. |+| 20 | B[7] | input | Input-only GPIO[23] pad that also serves as ADC_0 analog input AN[0] and RXD of LIN_0. |+| 21 | C[2] | input | Input-only GPIO[34] pad that also serves as ADC_0 analog input AN[3]. |+| 22 | B[8] | input | Input-only GPIO[24] pad that also serves as ADC_0 analog input AN[1] and ETC[5] of eTimer_0. |+| 23 | E[2] | input | Input-only GPIO[66] pad that also serves as ADC_0 analog input AN[5]. |+| 24 | B[9] | input | Input-only GPIO[25] pad that also serves as ADC_0 analog input AN[11]. |+| 25 | B[10] | input | Input-only GPIO[26] pad that also serves as ADC_0 analog input AN[12]. |+| 26 | B[11] | input | Input-only GPIO[27] pad that also serves as ADC_0 analog input AN[13]. |+| 27 | B[12] | input | Input-only GPIO[28] pad that also serves as ADC_0 analog input AN[14]. |+| 28 | VDD_HV_ADC0 | power_in | ADC_0 supply and high reference voltage (3.3 V or 5.0 V). |+| 29 | VSS_HV_ADC0 | power_in | ADC_0 ground and low reference voltage. |+| 30 | E[3]/B[13] | input | Input-only pad shared by GPIO[67] (ADC_0 AN[6]) and GPIO[29] (ADC_0 AN[6], RXD of LIN_1, emulated ADC_1 AN[0]). |+| 31 | BCTRL | passive | Voltage regulator external NPN ballast base control pin. |+| 32 | VDD_HV_REG | power_in | Voltage regulator supply voltage (3.3 V or 5.0 V); absolute maximum is -0.3 V to 6.0 V. |+| 33 | C[11] | bidirectional | GPIO[43] (port C, slow/medium pad) with ETC[4] of eTimer_0 and CS2 of DSPI_2 as alternate functions. |+| 34 | C[12] | bidirectional | GPIO[44] (port C, slow/medium pad) with ETC[5] of eTimer_0 and CS3 of DSPI_2 as alternate functions. |+| 35 | TDI | input | JTAG test data input, input only on a slow pad. |+| 36 | TMS | input | JTAG state machine control, input only on a slow pad. |+| 37 | TCK | input | JTAG test clock input, input only on a slow pad. |+| 38 | TDO | output | JTAG test data output on a slow pad (fast pad speed option when SRC = 1). |+| 39 | VSS_HV_IO2 | power_in | Input/output ground and data Flash memory HV ground. |+| 40 | VDD_HV_IO2 | power_in | Input/output supply voltage and data Flash memory supply voltage (3.3 V or 5.0 V). |+| 41 | A[3] | bidirectional | GPIO[3] (port A, slow/medium pad) with ETC[3], CS0, B[3], ABS[1] and EIRQ[3] as alternate functions. |+| 42 | VDD_LV_COR1 | power_in | 1.2 V supply for core logic and data Flash; the decoupling capacitor must be connected to the nearest VSS_LV_COR pin. |+| 43 | VSS_LV_COR1 | power_in | 1.2 V ground for core logic and data Flash; the decoupling capacitor must be connected to the nearest VDD_LV_COR pin. |+| 44 | D[13] | bidirectional | GPIO[61] (port D, slow/medium pad) with A[1] and FlexPWM_0 output as alternate functions. |+| 45 | D[12] | bidirectional | GPIO[60] (port D, slow/medium pad) with X[1] of FlexPWM_0 and RXD of LIN_1 as alternate functions. |+| 46 | D[14] | bidirectional | GPIO[62] (port D, slow/medium pad) with B[1] of FlexPWM_0 as alternate function. |+| 47 | VPP_TEST | input | Pin for testing purposes only; it must be tied to ground in normal operating mode. |+| 48 | A[4] | bidirectional | GPIO[4] (port A, slow/medium pad) with CS1, ETC[4] and EIRQ[4] as alternate functions. |+| 49 | B[0] | bidirectional | GPIO[16] (port B, slow/medium pad) with TXD of FlexCAN_0 and DEBUG[0] as alternate functions. |+| 50 | B[1] | bidirectional | GPIO[17] (port B, slow/medium pad) with RXD of FlexCAN_0 and DEBUG[1] as alternate functions. |+| 51 | B[2] | bidirectional | GPIO[18] (port B, slow/medium pad) with TXD of LIN_0 and DEBUG[2] as alternate functions. |+| 52 | A[10] | bidirectional | GPIO[10] (port A, slow/medium pad) with CS0, B[0], X[2] and EIRQ[9] as alternate functions. |+| 53 | A[11] | bidirectional | GPIO[11] (port A, slow/medium pad) with SCK of DSPI_2, A[0], A[2] and EIRQ[10] as alternate functions. |+| 54 | A[12] | bidirectional | GPIO[12] (port A, slow/medium pad) with SOUT of DSPI_2, A[2], B[2] and EIRQ[11] as alternate functions. |+| 55 | VDD_HV_IO3 | power_in | Input/output supply voltage and code Flash memory supply voltage (3.3 V or 5.0 V). |+| 56 | VSS_HV_IO3 | power_in | Input/output ground and code Flash memory HV ground. |+| 57 | C[8] | bidirectional | GPIO[40] (port C, slow/medium pad) with CS1 and CS6 of DSPI_0 as alternate functions. |+| 58 | VDD_LV_COR2 | power_in | 1.2 V supply for core logic and code Flash; the decoupling capacitor must be connected to the nearest VSS_LV_COR pin. |+| 59 | VSS_LV_COR2 | power_in | 1.2 V ground for core logic and code Flash; the decoupling capacitor must be connected to the nearest VDD_LV_COR pin. |+| 60 | A[9] | bidirectional | GPIO[9] (port A, slow/medium pad) with CS1, B[3] and FAULT[0] as alternate functions. |+| 61 | A[13] | bidirectional | GPIO[13] (port A, slow/medium pad) with B[2], SIN of DSPI_2, FAULT[0] and EIRQ[12] as alternate functions. |+| 62 | B[6] | bidirectional | GPIO[22] (port B, slow/medium pad) with CLKOUT, CS2 of DSPI_2 and EIRQ[18] as alternate functions. |+| 63 | A[14] | bidirectional | GPIO[14] (port A, slow/medium pad) with TXD of Safety Port_0 and EIRQ[13] as alternate functions. |+| 64 | A[15] | bidirectional | GPIO[15] (port A, slow/medium pad) with RXD of Safety Port_0 and EIRQ[14] as alternate functions. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-64(10x10) |+| Category | Embedded Processors & Controllers |+| Pins | 64 |++## CAD (KiCad official)++- Symbol: `SPC560P40L1CEFBR`+- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`+- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)+- 3D model files: `spc560p40l1cefbr-etched.step` / `spc560p40l1cefbr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `spc560p40l1cefbr.step` / `spc560p40l1cefbr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922392714756096) (103 pp, sha256 `277aabac54ee58c6`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/spc560p40l1cefbr-datasheet.pdf)
page.jsonadded+536@@ -0,0 +1,536 @@+{+ "slug": "spc560p40l1cefbr",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "spc560p40l1cefbr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "spc560p40l1cefbr.kicad_sym",+ "spc560p40l1cefbr.kicad_mod",+ "spc560p40l1cefbr.glb",+ "spc560p40l1cefbr.step",+ "spc560p40l1cefbr.lbr",+ "docs/hero.png",+ "docs/spc560p40l1cefbr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "spc560p40l1cefbr-hero.glb",+ "spc560p40l1cefbr-hero.overlay.json"+ ],+ "component": {+ "mpn": "SPC560P40L1CEFBR",+ "manufacturer": "STMicroelectronics",+ "package": "LQFP-64(10x10)",+ "pin_count": 64,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922392714756096",+ "parts": {+ "symbol": "spc560p40l1cefbr.kicad_sym",+ "footprint": "spc560p40l1cefbr.kicad_mod",+ "model_3d": "spc560p40l1cefbr-hero.glb",+ "model_3d_plain": "spc560p40l1cefbr.glb",+ "model_3d_step": "spc560p40l1cefbr-etched.step",+ "model_3d_step_plain": "spc560p40l1cefbr.step",+ "lbr": "spc560p40l1cefbr.lbr"+ },+ "distributor_links": {+ "lcsc": "C1342237",+ "digikey": "497-19301-2-ND",+ "mouser": "511-SPC560P40L1CEFBR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T19:12:55Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-19301-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-SPC560P40L1CEFBR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "NMI",+ "type": "input",+ "description": "Non-maskable interrupt input only, on a slow pad."+ },+ {+ "number": "2",+ "name": "A[6]",+ "type": "bidirectional",+ "description": "GPIO[6] (port A, slow/medium pad) with SCK of DSPI_1 and EIRQ[6] as alternate functions."+ },+ {+ "number": "3",+ "name": "A[7]",+ "type": "bidirectional",+ "description": "GPIO[7] (port A, slow/medium pad) with SOUT of DSPI_1 and EIRQ[7] as alternate functions."+ },+ {+ "number": "4",+ "name": "A[8]",+ "type": "bidirectional",+ "description": "GPIO[8] (port A, slow/medium pad) with SIN of DSPI_1 and EIRQ[8] as alternate functions."+ },+ {+ "number": "5",+ "name": "A[5]",+ "type": "bidirectional",+ "description": "GPIO[5] (port A, slow/medium pad) with CS0 and CS7 chip-select functions and EIRQ[5] as alternate functions."+ },+ {+ "number": "6",+ "name": "VDD_HV_IO1",+ "type": "power_in",+ "description": "3.3 V or 5.0 V input/output supply voltage; absolute maximum range is -0.3 V to 6.0 V."+ },+ {+ "number": "7",+ "name": "VSS_HV_IO1",+ "type": "power_in",+ "description": "Input/output ground for the VDD_HV_IO1 segment."+ },+ {+ "number": "8",+ "name": "D[9]",+ "type": "bidirectional",+ "description": "GPIO[57] (port D, slow/medium pad) with X[0] of FlexPWM_0 and TXD of LIN_1 as alternate functions."+ },+ {+ "number": "9",+ "name": "VDD_HV_OSC",+ "type": "power_in",+ "description": "3.3 V or 5.0 V crystal oscillator amplifier supply voltage."+ },+ {+ "number": "10",+ "name": "VSS_HV_OSC",+ "type": "power_in",+ "description": "Crystal oscillator amplifier ground."+ },+ {+ "number": "11",+ "name": "XTAL",+ "type": "passive",+ "description": "Analog output of the oscillator amplifier circuit; it must be grounded if the oscillator is used in bypass mode."+ },+ {+ "number": "12",+ "name": "EXTAL",+ "type": "input",+ "description": "Analog input of the oscillator amplifier circuit when not in bypass mode, and analog clock input when the oscillator is in bypass mode."+ },+ {+ "number": "13",+ "name": "RESET",+ "type": "bidirectional",+ "description": "Bidirectional reset pin with Schmitt trigger characteristics and noise filter."+ },+ {+ "number": "14",+ "name": "D[8]",+ "type": "bidirectional",+ "description": "GPIO[56] (port D, slow/medium pad) with CS2 and CS5 chip-select functions as alternate functions."+ },+ {+ "number": "15",+ "name": "VSS_LV_COR0",+ "type": "power_in",+ "description": "1.2 V ground for core logic and PLL; the decoupling capacitor must be connected to the nearest VDD_LV_COR pin."+ },+ {+ "number": "16",+ "name": "VDD_LV_COR0",+ "type": "power_in",+ "description": "1.2 V supply for core logic and PLL; the decoupling capacitor must be connected to the nearest VSS_LV_COR pin."+ },+ {+ "number": "17",+ "name": "D[7]",+ "type": "bidirectional",+ "description": "GPIO[55] (port D, slow/medium pad) with CS3, CS4, and F[1] of FCU_0 as alternate functions."+ },+ {+ "number": "18",+ "name": "E[1]",+ "type": "input",+ "description": "Input-only GPIO[65] pad that also serves as ADC_0 analog input AN[4]."+ },+ {+ "number": "19",+ "name": "C[1]",+ "type": "input",+ "description": "Input-only GPIO[33] pad that also serves as ADC_0 analog input AN[2]."+ },+ {+ "number": "20",+ "name": "B[7]",+ "type": "input",+ "description": "Input-only GPIO[23] pad that also serves as ADC_0 analog input AN[0] and RXD of LIN_0."+ },+ {+ "number": "21",+ "name": "C[2]",+ "type": "input",+ "description": "Input-only GPIO[34] pad that also serves as ADC_0 analog input AN[3]."+ },+ {+ "number": "22",+ "name": "B[8]",+ "type": "input",+ "description": "Input-only GPIO[24] pad that also serves as ADC_0 analog input AN[1] and ETC[5] of eTimer_0."+ },+ {+ "number": "23",+ "name": "E[2]",+ "type": "input",+ "description": "Input-only GPIO[66] pad that also serves as ADC_0 analog input AN[5]."+ },+ {+ "number": "24",+ "name": "B[9]",+ "type": "input",+ "description": "Input-only GPIO[25] pad that also serves as ADC_0 analog input AN[11]."+ },+ {+ "number": "25",+ "name": "B[10]",+ "type": "input",+ "description": "Input-only GPIO[26] pad that also serves as ADC_0 analog input AN[12]."+ },+ {+ "number": "26",+ "name": "B[11]",+ "type": "input",+ "description": "Input-only GPIO[27] pad that also serves as ADC_0 analog input AN[13]."+ },+ {+ "number": "27",+ "name": "B[12]",+ "type": "input",+ "description": "Input-only GPIO[28] pad that also serves as ADC_0 analog input AN[14]."+ },+ {+ "number": "28",+ "name": "VDD_HV_ADC0",+ "type": "power_in",+ "description": "ADC_0 supply and high reference voltage (3.3 V or 5.0 V)."+ },+ {+ "number": "29",+ "name": "VSS_HV_ADC0",+ "type": "power_in",+ "description": "ADC_0 ground and low reference voltage."+ },+ {+ "number": "30",+ "name": "E[3]/B[13]",+ "type": "input",+ "description": "Input-only pad shared by GPIO[67] (ADC_0 AN[6]) and GPIO[29] (ADC_0 AN[6], RXD of LIN_1, emulated ADC_1 AN[0])."+ },+ {+ "number": "31",+ "name": "BCTRL",+ "type": "passive",+ "description": "Voltage regulator external NPN ballast base control pin."+ },+ {+ "number": "32",+ "name": "VDD_HV_REG",+ "type": "power_in",+ "description": "Voltage regulator supply voltage (3.3 V or 5.0 V); absolute maximum is -0.3 V to 6.0 V."+ },+ {+ "number": "33",+ "name": "C[11]",+ "type": "bidirectional",+ "description": "GPIO[43] (port C, slow/medium pad) with ETC[4] of eTimer_0 and CS2 of DSPI_2 as alternate functions."+ },+ {+ "number": "34",+ "name": "C[12]",+ "type": "bidirectional",+ "description": "GPIO[44] (port C, slow/medium pad) with ETC[5] of eTimer_0 and CS3 of DSPI_2 as alternate functions."+ },+ {+ "number": "35",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input, input only on a slow pad."+ },+ {+ "number": "36",+ "name": "TMS",+ "type": "input",+ "description": "JTAG state machine control, input only on a slow pad."+ },+ {+ "number": "37",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock input, input only on a slow pad."+ },+ {+ "number": "38",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output on a slow pad (fast pad speed option when SRC = 1)."+ },+ {+ "number": "39",+ "name": "VSS_HV_IO2",+ "type": "power_in",+ "description": "Input/output ground and data Flash memory HV ground."+ },+ {+ "number": "40",+ "name": "VDD_HV_IO2",+ "type": "power_in",+ "description": "Input/output supply voltage and data Flash memory supply voltage (3.3 V or 5.0 V)."+ },+ {+ "number": "41",+ "name": "A[3]",+ "type": "bidirectional",+ "description": "GPIO[3] (port A, slow/medium pad) with ETC[3], CS0, B[3], ABS[1] and EIRQ[3] as alternate functions."+ },+ {+ "number": "42",+ "name": "VDD_LV_COR1",+ "type": "power_in",+ "description": "1.2 V supply for core logic and data Flash; the decoupling capacitor must be connected to the nearest VSS_LV_COR pin."+ },+ {+ "number": "43",+ "name": "VSS_LV_COR1",+ "type": "power_in",+ "description": "1.2 V ground for core logic and data Flash; the decoupling capacitor must be connected to the nearest VDD_LV_COR pin."+ },+ {+ "number": "44",+ "name": "D[13]",+ "type": "bidirectional",+ "description": "GPIO[61] (port D, slow/medium pad) with A[1] and FlexPWM_0 output as alternate functions."+ },+ {+ "number": "45",+ "name": "D[12]",+ "type": "bidirectional",+ "description": "GPIO[60] (port D, slow/medium pad) with X[1] of FlexPWM_0 and RXD of LIN_1 as alternate functions."+ },+ {+ "number": "46",+ "name": "D[14]",+ "type": "bidirectional",+ "description": "GPIO[62] (port D, slow/medium pad) with B[1] of FlexPWM_0 as alternate function."+ },+ {+ "number": "47",+ "name": "VPP_TEST",+ "type": "input",+ "description": "Pin for testing purposes only; it must be tied to ground in normal operating mode."+ },+ {+ "number": "48",+ "name": "A[4]",+ "type": "bidirectional",+ "description": "GPIO[4] (port A, slow/medium pad) with CS1, ETC[4] and EIRQ[4] as alternate functions."+ },+ {+ "number": "49",+ "name": "B[0]",+ "type": "bidirectional",+ "description": "GPIO[16] (port B, slow/medium pad) with TXD of FlexCAN_0 and DEBUG[0] as alternate functions."+ },+ {+ "number": "50",+ "name": "B[1]",+ "type": "bidirectional",+ "description": "GPIO[17] (port B, slow/medium pad) with RXD of FlexCAN_0 and DEBUG[1] as alternate functions."+ },+ {+ "number": "51",+ "name": "B[2]",+ "type": "bidirectional",+ "description": "GPIO[18] (port B, slow/medium pad) with TXD of LIN_0 and DEBUG[2] as alternate functions."+ },+ {+ "number": "52",+ "name": "A[10]",+ "type": "bidirectional",+ "description": "GPIO[10] (port A, slow/medium pad) with CS0, B[0], X[2] and EIRQ[9] as alternate functions."+ },+ {+ "number": "53",+ "name": "A[11]",+ "type": "bidirectional",+ "description": "GPIO[11] (port A, slow/medium pad) with SCK of DSPI_2, A[0], A[2] and EIRQ[10] as alternate functions."+ },+ {+ "number": "54",+ "name": "A[12]",+ "type": "bidirectional",+ "description": "GPIO[12] (port A, slow/medium pad) with SOUT of DSPI_2, A[2], B[2] and EIRQ[11] as alternate functions."+ },+ {+ "number": "55",+ "name": "VDD_HV_IO3",+ "type": "power_in",+ "description": "Input/output supply voltage and code Flash memory supply voltage (3.3 V or 5.0 V)."+ },+ {+ "number": "56",+ "name": "VSS_HV_IO3",+ "type": "power_in",+ "description": "Input/output ground and code Flash memory HV ground."+ },+ {+ "number": "57",+ "name": "C[8]",+ "type": "bidirectional",+ "description": "GPIO[40] (port C, slow/medium pad) with CS1 and CS6 of DSPI_0 as alternate functions."+ },+ {+ "number": "58",+ "name": "VDD_LV_COR2",+ "type": "power_in",+ "description": "1.2 V supply for core logic and code Flash; the decoupling capacitor must be connected to the nearest VSS_LV_COR pin."+ },+ {+ "number": "59",+ "name": "VSS_LV_COR2",+ "type": "power_in",+ "description": "1.2 V ground for core logic and code Flash; the decoupling capacitor must be connected to the nearest VDD_LV_COR pin."+ },+ {+ "number": "60",+ "name": "A[9]",+ "type": "bidirectional",+ "description": "GPIO[9] (port A, slow/medium pad) with CS1, B[3] and FAULT[0] as alternate functions."+ },+ {+ "number": "61",+ "name": "A[13]",+ "type": "bidirectional",+ "description": "GPIO[13] (port A, slow/medium pad) with B[2], SIN of DSPI_2, FAULT[0] and EIRQ[12] as alternate functions."+ },+ {+ "number": "62",+ "name": "B[6]",+ "type": "bidirectional",+ "description": "GPIO[22] (port B, slow/medium pad) with CLKOUT, CS2 of DSPI_2 and EIRQ[18] as alternate functions."+ },+ {+ "number": "63",+ "name": "A[14]",+ "type": "bidirectional",+ "description": "GPIO[14] (port A, slow/medium pad) with TXD of Safety Port_0 and EIRQ[13] as alternate functions."+ },+ {+ "number": "64",+ "name": "A[15]",+ "type": "bidirectional",+ "description": "GPIO[15] (port A, slow/medium pad) with RXD of Safety Port_0 and EIRQ[14] as alternate functions."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: MPN decoding: SPC560P40L1CEFBR = SPC56 0P 40 L1 C E F B R -> 256 KB code flash, LQFP64, -40 to 125 C; The figure text extraction does not preserve pin numbers in order. Pin numbers were assigned by matc; Pin types are KiCad ERC classes chosen from the datasheet pad descriptions. Supplies are power_in; G"+ ],+ "pages_sent": 32,+ "cost_usd": 0.2294,+ "at": "2026-10-08T19:12:26"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588922392714756096",+ "pages": 103,+ "sha256": "277aabac54ee58c6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 64,+ "described": 64,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "spc560p40l1cefbr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b0c827bc5c05552175d28affe44a5bd2ab45c9c36efff6ff07a74cc449b13db4",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "spc560p40l1cefbr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 12,+ 12,+ 1.5+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "b42884710fb77e042a6f0a85dc7229808cc627ca280be31a9147a4ae3d4a0084",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}