component
SPC560B50L5C6E0X
Public Made by Adomby adom
STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+180@@ -0,0 +1,180 @@+# SPC560B50L5C6E0X++**STMicroelectronics** · Microcontrollers (MCU/MPU/SOC) · LQFP-144(20x20)++SPC560B50L5C6E0X from STMicroelectronics, in a LQFP-144(20x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | PB[3] | input | GPIO[19] or LINFlex_0 receiver; Schmitt trigger input with weak pull-up during reset. |+| 2 | PC[9] | input | GPIO[41] or LINFlex_2 receiver; Schmitt trigger input with wakeup capability. |+| 3 | PC[14] | bidirectional | GPIO[46] or eMIOS_0 channel E0UC[14] or DSPI_2 serial clock; medium slew rate output buffer. |+| 4 | PC[15] | bidirectional | GPIO[47] or eMIOS_0 channel E0UC[15] or DSPI_2 chip select; medium slew rate output buffer. |+| 5 | PG[5] | input | GPIO[101] or eMIOS_1 channel E1UC[14] or wakeup input WKPU[18]; Schmitt trigger input. |+| 6 | PG[4] | bidirectional | GPIO[100] or eMIOS_1 channel E1UC[13]; medium slew rate output buffer. |+| 7 | PG[3] | input | GPIO[99] or eMIOS_1 channel E1UC[12] or wakeup input WKPU[17]; Schmitt trigger input. |+| 8 | PG[2] | bidirectional | GPIO[98] or eMIOS_1 channel E1UC[11]; medium slew rate output buffer. |+| 9 | PA[2] | input | GPIO[2] or eMIOS_0 channel E0UC[2] or wakeup input WKPU[3]; Schmitt trigger input. |+| 10 | PE[0] | input | GPIO[64] or eMIOS_0 channel E0UC[16] or FlexCAN_5 receiver or wakeup input WKPU[6]; Schmitt trigger input. |+| 11 | PA[1] | input | GPIO[1] or eMIOS_0 channel E0UC[1] or non-maskable interrupt or wakeup input WKPU[2]; Schmitt trigger input. |+| 12 | PE[1] | bidirectional | GPIO[65] or eMIOS_0 channel E0UC[17] or FlexCAN_5 transmitter; medium slew rate output buffer. |+| 13 | PE[8] | bidirectional | GPIO[72] or FlexCAN_2 transmitter or eMIOS_0 channel E0UC[22] or FlexCAN_3 transmitter; medium slew rate output buffer. |+| 14 | PE[9] | input | GPIO[73] or eMIOS_0 channel E0UC[23] or wakeup input WKPU[7] or FlexCAN_2/3 receiver; Schmitt trigger input. |+| 15 | PE[10] | bidirectional | GPIO[74] or LINFlex_3 transmitter or DSPI_1 chip select; slow slew rate output buffer. |+| 16 | PA[0] | bidirectional | GPIO[0] or eMIOS_0 channel E0UC[0] or system clock output or wakeup input WKPU[19]; medium slew rate output buffer. |+| 17 | PE[11] | bidirectional | GPIO[75] or DSPI_1 chip select CS4_1 or LINFlex_3 receiver or wakeup input WKPU[14]; slow slew rate output buffer. |+| 18 | VSS_HV | power_in | Digital ground reference for high-voltage domain VDD_HV power supply. |+| 19 | VDD_HV | power_in | Digital supply voltage (3.3V or 5.0V nominal); 100nF ceramic capacitor required between VDD_HV and nearest VSS_HV pin. |+| 20 | VSS_HV | power_in | Digital ground reference for high-voltage domain VDD_HV power supply. |+| 21 | RESET | bidirectional | Bidirectional reset pin with Schmitt trigger and integrated noise filter for 1µs glitch rejection; requires external pull-up resistor. |+| 22 | VSS_LV | power_in | Low-voltage (1.2V) domain ground; 330nF ceramic capacitor required between nearest VDD_LV pin and this pin for regulator stability. |+| 23 | VDD_LV | power_in | Low-voltage (1.2V) internal regulator output; 330nF ceramic capacitor required between this pin and nearest VSS_LV pin for regulator stability. |+| 24 | VDD_BV | power_in | Internal voltage regulator ballast supply voltage (3.3V or 5.0V aligned with VDD); 100nF to 470nF decoupling capacitor required. |+| 25 | PG[9] | bidirectional | GPIO[105] or eMIOS_1 channel E1UC[18] or DSPI_2 serial clock; slow slew rate output buffer. |+| 26 | PG[8] | bidirectional | GPIO[104] or eMIOS_1 channel E1UC[17] or DSPI_2 chip select or external interrupt EIRQ[15]; slow slew rate output buffer. |+| 27 | PC[11] | input | GPIO[43] or FlexCAN_1 receiver or FlexCAN_4 receiver or wakeup input WKPU[5]; Schmitt trigger input. |+| 28 | PC[10] | bidirectional | GPIO[42] or FlexCAN_1 transmitter or FlexCAN_4 transmitter or ADC multiplexer control MA[1]; medium slew rate output buffer. |+| 29 | PG[7] | bidirectional | GPIO[103] or eMIOS_1 channel E1UC[16]; medium slew rate output buffer. |+| 30 | PG[6] | bidirectional | GPIO[102] or eMIOS_1 channel E1UC[15]; medium slew rate output buffer. |+| 31 | PB[0] | bidirectional | GPIO[16] or FlexCAN_0 transmitter; medium slew rate output buffer. |+| 32 | PB[1] | input | GPIO[17] or FlexCAN_0 receiver or wakeup input WKPU[4]; Schmitt trigger input. |+| 33 | PF[9] | bidirectional | GPIO[89] or DSPI_0 chip select CS5_0 or FlexCAN_2/3 receiver; slow slew rate output buffer. |+| 34 | PF[8] | bidirectional | GPIO[88] or FlexCAN_3 transmitter or DSPI_0 chip select CS4_0 or FlexCAN_2 transmitter; medium slew rate output buffer. |+| 35 | PF[12] | bidirectional | GPIO[92] or eMIOS_1 channel E1UC[25]; medium slew rate output buffer. |+| 36 | PC[6] | bidirectional | GPIO[38] or LINFlex_1 transmitter; slow slew rate output buffer. |+| 37 | PC[7] | input | GPIO[39] or LINFlex_1 receiver or wakeup input WKPU[12]; Schmitt trigger input. |+| 38 | PF[10] | bidirectional | GPIO[90]; medium slew rate output buffer. |+| 39 | PF[11] | input | GPIO[91] or wakeup input WKPU[15]; Schmitt trigger input. |+| 40 | PA[15] | bidirectional | GPIO[15] or DSPI_0 chip select CS0_0 or serial clock SCK_0 or wakeup input WKPU[10]; medium slew rate output buffer. |+| 41 | PF[13] | input | GPIO[93] or eMIOS_1 channel E1UC[26] or wakeup input WKPU[16]; Schmitt trigger input. |+| 42 | PA[14] | bidirectional | GPIO[14] or DSPI_0 serial clock SCK_0 or chip select CS0_0 or external interrupt EIRQ[4]; medium slew rate output buffer. |+| 43 | PA[4] | input | GPIO[4] or eMIOS_0 channel E0UC[4] or wakeup input WKPU[9]; Schmitt trigger input. |+| 44 | PA[13] | bidirectional | GPIO[13] or DSPI_0 serial data output; medium slew rate output buffer. |+| 45 | PA[12] | input | GPIO[12] or DSPI_0 serial data input; Schmitt trigger input. |+| 46 | VDD_LV | power_in | Low-voltage (1.2V) internal regulator output; 330nF ceramic capacitor required between this pin and nearest VSS_LV pin for regulator stability. |+| 47 | VSS_LV | power_in | Low-voltage (1.2V) domain ground; 330nF ceramic capacitor required between nearest VDD_LV pin and this pin for regulator stability. |+| 48 | XTAL | bidirectional | External crystal oscillator input requiring connection to ground if oscillator is operated in bypass mode; part of 4-16MHz crystal oscillator circuit. |+| 49 | VSS_HV | power_in | Digital ground reference for high-voltage domain VDD_HV power supply. |+| 50 | EXTAL | bidirectional | External crystal oscillator amplifier output in normal oscillator mode or analog clock input in bypass mode; part of 4-16MHz crystal oscillator circuit. |+| 51 | VDD_HV | power_in | Digital supply voltage (3.3V or 5.0V nominal); 100nF ceramic capacitor required between VDD_HV and nearest VSS_HV pin. |+| 52 | PB[9] | bidirectional | GPIO[25] or 32kHz slow external crystal oscillator EXTAL or ADC channel ANS[1]; fast input-only analog pad. |+| 53 | PB[8] | bidirectional | GPIO[24] or 32kHz slow external crystal oscillator XTAL or ADC channel ANS[0]; fast input-only analog pad. |+| 54 | PB[10] | bidirectional | GPIO[26] or ADC channel ANS[2] or wakeup input WKPU[8]; J-type pad with analog feature. |+| 55 | PF[0] | bidirectional | GPIO[80] or eMIOS_0 channel E0UC[10] or DSPI_1 chip select CS3_0 or ADC channel ANS[8]; J-type pad with analog feature. |+| 56 | PF[1] | bidirectional | GPIO[81] or eMIOS_0 channel E0UC[11] or DSPI_1 chip select CS4_0 or ADC channel ANS[9]; J-type pad with analog feature. |+| 57 | PF[2] | bidirectional | GPIO[82] or eMIOS_0 channel E0UC[12] or DSPI_2 chip select CS0_2 or ADC channel ANS[10]; J-type pad with analog feature. |+| 58 | PF[3] | bidirectional | GPIO[83] or eMIOS_0 channel E0UC[13] or DSPI_2 chip select CS1_2 or ADC channel ANS[11]; J-type pad with analog feature. |+| 59 | PF[4] | bidirectional | GPIO[84] or eMIOS_0 channel E0UC[14] or DSPI_2 chip select CS2_2 or ADC channel ANS[12]; J-type pad with analog feature. |+| 60 | PF[5] | bidirectional | GPIO[85] or eMIOS_0 channel E0UC[22] or DSPI_2 chip select CS3_2 or ADC channel ANS[13]; J-type pad with analog feature. |+| 61 | PF[6] | bidirectional | GPIO[86] or eMIOS_0 channel E0UC[23] or ADC channel ANS[14]; J-type pad with analog feature. |+| 62 | PF[7] | bidirectional | GPIO[87] or ADC channel ANS[15]; J-type pad with analog feature. |+| 63 | PD[0] | input | GPIO[48] or ADC precise channel GPI[4]; fast input-only pad without output buffer. |+| 64 | PD[1] | input | GPIO[49] or ADC precise channel GPI[5]; fast input-only pad without output buffer. |+| 65 | PD[2] | input | GPIO[50] or ADC precise channel GPI[6]; fast input-only pad without output buffer. |+| 66 | PD[3] | input | GPIO[51] or ADC precise channel GPI[7]; fast input-only pad without output buffer. |+| 67 | PD[4] | input | GPIO[52] or ADC precise channel GPI[8]; fast input-only pad without output buffer. |+| 68 | PD[5] | input | GPIO[53] or ADC precise channel GPI[9]; fast input-only pad without output buffer. |+| 69 | PD[6] | input | GPIO[54] or ADC precise channel GPI[10]; fast input-only pad without output buffer. |+| 70 | PD[7] | input | GPIO[55] or ADC precise channel GPI[11]; fast input-only pad without output buffer. |+| 71 | PD[8] | input | GPIO[56] or ADC precise channel GPI[12]; fast input-only pad without output buffer. |+| 72 | PB[4] | input | GPIO[20] or ADC precise channel GPI[0]; fast input-only pad without output buffer. |+| 73 | VSS_HV_ADC | power_in | ADC reference ground and analog ground; must be connected to VSS_HV externally to ensure common ground. |+| 74 | VDD_HV_ADC | power_in | ADC reference voltage supply; 1µF electrolytic + 47nF ceramic capacitor required between VDD_HV_ADC and VSS_HV_ADC for ADC accuracy. |+| 75 | PB[5] | input | GPIO[21] or ADC precise channel GPI[1]; fast input-only pad without output buffer. |+| 76 | PB[6] | input | GPIO[22] or ADC precise channel GPI[2]; fast input-only pad without output buffer. |+| 77 | PB[7] | input | GPIO[23] or ADC precise channel GPI[3]; fast input-only pad without output buffer. |+| 78 | PD[9] | input | GPIO[57] or ADC precise channel GPI[13]; fast input-only pad without output buffer. |+| 79 | PD[10] | input | GPIO[58] or ADC precise channel GPI[14]; fast input-only pad without output buffer. |+| 80 | PD[11] | input | GPIO[59] or ADC precise channel GPI[15]; fast input-only pad without output buffer. |+| 81 | PB[11] | bidirectional | GPIO[27] or eMIOS_0 channel E0UC[3] or DSPI_0 chip select CS0_0 or ADC channel ANS[3]; J-type pad with analog feature. |+| 82 | PD[12] | bidirectional | GPIO[60] or DSPI_0 chip select CS5_0 or eMIOS_0 channel E0UC[24] or ADC channel ANS[4]; J-type pad with analog feature. |+| 83 | PB[12] | bidirectional | GPIO[28] or eMIOS_0 channel E0UC[4] or DSPI_0 chip select CS1_0 or ADC extended channel ANX[0]; J-type pad with analog feature. |+| 84 | PD[13] | bidirectional | GPIO[61] or DSPI_1 chip select CS0_1 or eMIOS_0 channel E0UC[25] or ADC channel ANS[5]; J-type pad with analog feature. |+| 85 | PB[13] | bidirectional | GPIO[29] or eMIOS_0 channel E0UC[5] or DSPI_0 chip select CS2_0 or ADC extended channel ANX[1]; J-type pad with analog feature. |+| 86 | PD[14] | bidirectional | GPIO[62] or DSPI_1 chip select CS1_1 or eMIOS_0 channel E0UC[26] or ADC channel ANS[6]; J-type pad with analog feature. |+| 87 | PB[14] | bidirectional | GPIO[30] or eMIOS_0 channel E0UC[6] or DSPI_0 chip select CS3_0 or ADC extended channel ANX[2]; J-type pad with analog feature. |+| 88 | PD[15] | bidirectional | GPIO[63] or DSPI_1 chip select CS2_1 or eMIOS_0 channel E0UC[27] or ADC channel ANS[7]; J-type pad with analog feature. |+| 89 | PB[15] | bidirectional | GPIO[31] or eMIOS_0 channel E0UC[7] or DSPI_0 chip select CS4_0 or ADC extended channel ANX[3]; J-type pad with analog feature. |+| 90 | PA[3] | input | GPIO[3] or eMIOS_0 channel E0UC[3] or external interrupt EIRQ[0]; Schmitt trigger input. |+| 91 | PG[13] | bidirectional | GPIO[109] or eMIOS_0 channel E0UC[27]; medium slew rate output buffer. |+| 92 | PG[12] | bidirectional | GPIO[108] or eMIOS_0 channel E0UC[26]; medium slew rate output buffer. |+| 93 | PH[0] | bidirectional | GPIO[112] or eMIOS_1 channel E1UC[2] or DSPI_1 serial data input; medium slew rate output buffer. |+| 94 | PH[1] | bidirectional | GPIO[113] or eMIOS_1 channel E1UC[3] or DSPI_1 serial data output; medium slew rate output buffer. |+| 95 | PH[2] | bidirectional | GPIO[114] or eMIOS_1 channel E1UC[4] or DSPI_1 serial clock; medium slew rate output buffer. |+| 96 | PH[3] | bidirectional | GPIO[115] or eMIOS_1 channel E1UC[5] or DSPI_1 chip select CS0_1; medium slew rate output buffer. |+| 97 | PG[1] | input | GPIO[97] or eMIOS_1 channel E1UC[24] or FlexCAN_5 receiver or external interrupt EIRQ[14]; Schmitt trigger input. |+| 98 | PG[0] | bidirectional | GPIO[96] or FlexCAN_5 transmitter or eMIOS_1 channel E1UC[23]; medium slew rate output buffer. |+| 99 | VSS_HV | power_in | Digital ground reference for high-voltage domain VDD_HV power supply. |+| 100 | VDD_HV | power_in | Digital supply voltage (3.3V or 5.0V nominal); 100nF ceramic capacitor required between VDD_HV and nearest VSS_HV pin. |+| 101 | PF[15] | input | GPIO[95] or FlexCAN_1 receiver or FlexCAN_4 receiver or external interrupt EIRQ[13]; Schmitt trigger input. |+| 102 | PF[14] | bidirectional | GPIO[94] or FlexCAN_4 transmitter or eMIOS_1 channel E1UC[27] or FlexCAN_1 transmitter; medium slew rate output buffer. |+| 103 | PE[13] | bidirectional | GPIO[77] or DSPI_2 serial data output or eMIOS_1 channel E1UC[20]; slow slew rate output buffer. |+| 104 | PA[7] | bidirectional | GPIO[7] or eMIOS_0 channel E0UC[7] or LINFlex_3 transmitter or external interrupt EIRQ[2]; slow slew rate output buffer. |+| 105 | PA[8] | bidirectional | GPIO[8] or eMIOS_0 channel E0UC[8] or external interrupt EIRQ[3] or boot mode FAB pin or LINFlex_3 receiver; weak pull-up after reset. |+| 106 | PA[9] | bidirectional | GPIO[9] or eMIOS_0 channel E0UC[9] or boot mode FAB pin (pull-down during reset); slow slew rate output buffer. |+| 107 | PA[10] | bidirectional | GPIO[10] or eMIOS_0 channel E0UC[10] or I2C_0 SDA (open-drain); slow slew rate output buffer. |+| 108 | PA[11] | bidirectional | GPIO[11] or eMIOS_0 channel E0UC[11] or I2C_0 SCL (open-drain); slow slew rate output buffer. |+| 109 | PE[12] | bidirectional | GPIO[76] or DSPI_2 serial data input or external interrupt EIRQ[11]; medium slew rate output buffer. |+| 110 | PG[14] | bidirectional | GPIO[110] or eMIOS_1 channel E1UC[0]; slow slew rate output buffer. |+| 111 | PG[15] | bidirectional | GPIO[111] or eMIOS_1 channel E1UC[1]; medium slew rate output buffer. |+| 112 | PE[14] | bidirectional | GPIO[78] or DSPI_2 serial clock or eMIOS_1 channel E1UC[21] or external interrupt EIRQ[12]; slow slew rate output buffer. |+| 113 | PE[15] | bidirectional | GPIO[79] or DSPI_2 chip select CS0_2 or eMIOS_1 channel E1UC[22]; medium slew rate output buffer. |+| 114 | PG[10] | bidirectional | GPIO[106] or eMIOS_0 channel E0UC[24]; slow slew rate output buffer. |+| 115 | PG[11] | bidirectional | GPIO[107] or eMIOS_0 channel E0UC[25]; medium slew rate output buffer. |+| 116 | PC[3] | bidirectional | GPIO[35] or DSPI_1 chip select CS0_1 or ADC multiplexer MA[0] or FlexCAN_1 receiver or FlexCAN_4 receiver or external interrupt EIRQ[6]; slow slew rate output buffer. |+| 117 | PC[2] | bidirectional | GPIO[34] or DSPI_1 serial clock or FlexCAN_4 transmitter or external interrupt EIRQ[5]; medium slew rate output buffer. |+| 118 | PA[5] | bidirectional | GPIO[5] or eMIOS_0 channel E0UC[5]; medium slew rate output buffer. |+| 119 | PA[6] | input | GPIO[6] or eMIOS_0 channel E0UC[6] or external interrupt EIRQ[1]; Schmitt trigger input. |+| 120 | PH[10] | bidirectional | GPIO[122] or JTAG test mode select (TMS); weak pull-up input, slow slew rate output buffer. |+| 121 | PC[1] | bidirectional | GPIO[33] or JTAG test data output (TDO); external pull-up required in STANDBY mode, medium slew rate output buffer. |+| 122 | VSS_HV | power_in | Digital ground reference for high-voltage domain VDD_HV power supply. |+| 123 | VDD_HV | power_in | Digital supply voltage (3.3V or 5.0V nominal); 100nF ceramic capacitor required between VDD_HV and nearest VSS_HV pin. |+| 124 | VDD_LV | power_in | Low-voltage (1.2V) internal regulator output; 330nF ceramic capacitor required between this pin and nearest VSS_LV pin for regulator stability. |+| 125 | VSS_LV | power_in | Low-voltage (1.2V) domain ground; 330nF ceramic capacitor required between nearest VDD_LV pin and this pin for regulator stability. |+| 126 | PC[0] | bidirectional | GPIO[32] or JTAG test data input (TDI); weak pull-up input, medium slew rate output buffer. |+| 127 | PH[9] | bidirectional | GPIO[121] or JTAG test clock input (TCK); weak pull-up input, slow slew rate output buffer. |+| 128 | PE[2] | bidirectional | GPIO[66] or eMIOS_0 channel E0UC[18] or DSPI_1 serial data input; medium slew rate output buffer. |+| 129 | PE[3] | bidirectional | GPIO[67] or eMIOS_0 channel E0UC[19] or DSPI_1 serial data output; medium slew rate output buffer. |+| 130 | PC[5] | bidirectional | GPIO[37] or DSPI_1 serial data output or FlexCAN_3 transmitter or external interrupt EIRQ[7]; medium slew rate output buffer. |+| 131 | PC[4] | bidirectional | GPIO[36] or DSPI_1 serial data input or FlexCAN_3 receiver; medium slew rate output buffer. |+| 132 | PE[4] | bidirectional | GPIO[68] or eMIOS_0 channel E0UC[20] or DSPI_1 serial clock or external interrupt EIRQ[9]; medium slew rate output buffer. |+| 133 | PE[5] | bidirectional | GPIO[69] or eMIOS_0 channel E0UC[21] or DSPI_1 chip select CS0_1 or ADC multiplexer MA[2]; medium slew rate output buffer. |+| 134 | PH[4] | bidirectional | GPIO[116] or eMIOS_1 channel E1UC[6]; medium slew rate output buffer. |+| 135 | PH[5] | bidirectional | GPIO[117] or eMIOS_1 channel E1UC[7]; slow slew rate output buffer. |+| 136 | PH[6] | bidirectional | GPIO[118] or eMIOS_1 channel E1UC[8] or ADC multiplexer MA[2]; medium slew rate output buffer. |+| 137 | PH[7] | bidirectional | GPIO[119] or eMIOS_1 channel E1UC[9] or DSPI_2 chip select CS3_2 or ADC multiplexer MA[1]; medium slew rate output buffer. |+| 138 | PH[8] | bidirectional | GPIO[120] or eMIOS_1 channel E1UC[10] or DSPI_2 chip select CS2_2 or ADC multiplexer MA[0]; medium slew rate output buffer. |+| 139 | PE[6] | bidirectional | GPIO[70] or eMIOS_0 channel E0UC[22] or DSPI_0 chip select CS3_0 or ADC multiplexer MA[1]; medium slew rate output buffer. |+| 140 | PE[7] | bidirectional | GPIO[71] or eMIOS_0 channel E0UC[23] or DSPI_0 chip select CS2_0 or ADC multiplexer MA[0]; medium slew rate output buffer. |+| 141 | PC[12] | bidirectional | GPIO[44] or eMIOS_0 channel E0UC[12] or DSPI_2 serial data input; medium slew rate output buffer. |+| 142 | PC[13] | bidirectional | GPIO[45] or eMIOS_0 channel E0UC[13] or DSPI_2 serial data output; slow slew rate output buffer. |+| 143 | PC[8] | bidirectional | GPIO[40] or LINFlex_2 transmitter; slow slew rate output buffer. |+| 144 | PB[2] | bidirectional | GPIO[18] or LINFlex_0 transmitter or I2C_0 SDA (open-drain); medium slew rate output buffer. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | LQFP-144(20x20) |+| Category | Embedded Processors & Controllers |+| Pins | 144 |++## CAD (KiCad official)++- Symbol: `SPC560B50L5C6E0X`+- Footprint: `Package_QFP:LQFP-144_20x20mm_P0.5mm`+- 3D model: LQFP-144(20x20) (KiCad packages3D, STEP)+- 3D model files: `spc560b50l5c6e0x-etched.step` / `spc560b50l5c6e0x-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `spc560b50l5c6e0x.step` / `spc560b50l5c6e0x.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8584346429225095168) (116 pp, sha256 `17b37543a9b5ee31`, retrieved 2026-09-30, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/spc560b50l5c6e0x-datasheet.pdf)
page.jsonadded+974@@ -0,0 +1,974 @@+{+ "slug": "spc560b50l5c6e0x",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Microcontrollers (MCU/MPU/SOC), LQFP-144(20x20). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "spc560b50l5c6e0x",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "spc560b50l5c6e0x.kicad_sym",+ "spc560b50l5c6e0x.kicad_mod",+ "spc560b50l5c6e0x.glb",+ "spc560b50l5c6e0x.step",+ "spc560b50l5c6e0x.lbr",+ "docs/hero.png",+ "docs/spc560b50l5c6e0x-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "SPC560B50L5C6E0X",+ "manufacturer": "STMicroelectronics",+ "package": "LQFP-144(20x20)",+ "pin_count": 144,+ "category": "Embedded Processors & Controllers",+ "subcategory": "Microcontrollers (MCU/MPU/SOC)",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8584346429225095168",+ "parts": {+ "symbol": "spc560b50l5c6e0x.kicad_sym",+ "footprint": "spc560b50l5c6e0x.kicad_mod",+ "model_3d": "spc560b50l5c6e0x-etched.glb",+ "model_3d_plain": "spc560b50l5c6e0x.glb",+ "model_3d_step": "spc560b50l5c6e0x-etched.step",+ "model_3d_step_plain": "spc560b50l5c6e0x.step",+ "lbr": "spc560b50l5c6e0x.lbr"+ },+ "distributor_links": {+ "lcsc": "C2055653",+ "digikey": "497-11609-2-ND",+ "mouser": "511-SPC560B50L5C6E0X"+ },+ "distributor_check": {+ "checked_at": "2026-09-30T01:48:52Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-11609-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "511-SPC560B50L5C6E0X",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "PB[3]",+ "type": "input",+ "description": "GPIO[19] or LINFlex_0 receiver; Schmitt trigger input with weak pull-up during reset."+ },+ {+ "number": "2",+ "name": "PC[9]",+ "type": "input",+ "description": "GPIO[41] or LINFlex_2 receiver; Schmitt trigger input with wakeup capability."+ },+ {+ "number": "3",+ "name": "PC[14]",+ "type": "bidirectional",+ "description": "GPIO[46] or eMIOS_0 channel E0UC[14] or DSPI_2 serial clock; medium slew rate output buffer."+ },+ {+ "number": "4",+ "name": "PC[15]",+ "type": "bidirectional",+ "description": "GPIO[47] or eMIOS_0 channel E0UC[15] or DSPI_2 chip select; medium slew rate output buffer."+ },+ {+ "number": "5",+ "name": "PG[5]",+ "type": "input",+ "description": "GPIO[101] or eMIOS_1 channel E1UC[14] or wakeup input WKPU[18]; Schmitt trigger input."+ },+ {+ "number": "6",+ "name": "PG[4]",+ "type": "bidirectional",+ "description": "GPIO[100] or eMIOS_1 channel E1UC[13]; medium slew rate output buffer."+ },+ {+ "number": "7",+ "name": "PG[3]",+ "type": "input",+ "description": "GPIO[99] or eMIOS_1 channel E1UC[12] or wakeup input WKPU[17]; Schmitt trigger input."+ },+ {+ "number": "8",+ "name": "PG[2]",+ "type": "bidirectional",+ "description": "GPIO[98] or eMIOS_1 channel E1UC[11]; medium slew rate output buffer."+ },+ {+ "number": "9",+ "name": "PA[2]",+ "type": "input",+ "description": "GPIO[2] or eMIOS_0 channel E0UC[2] or wakeup input WKPU[3]; Schmitt trigger input."+ },+ {+ "number": "10",+ "name": "PE[0]",+ "type": "input",+ "description": "GPIO[64] or eMIOS_0 channel E0UC[16] or FlexCAN_5 receiver or wakeup input WKPU[6]; Schmitt trigger input."+ },+ {+ "number": "11",+ "name": "PA[1]",+ "type": "input",+ "description": "GPIO[1] or eMIOS_0 channel E0UC[1] or non-maskable interrupt or wakeup input WKPU[2]; Schmitt trigger input."+ },+ {+ "number": "12",+ "name": "PE[1]",+ "type": "bidirectional",+ "description": "GPIO[65] or eMIOS_0 channel E0UC[17] or FlexCAN_5 transmitter; medium slew rate output buffer."+ },+ {+ "number": "13",+ "name": "PE[8]",+ "type": "bidirectional",+ "description": "GPIO[72] or FlexCAN_2 transmitter or eMIOS_0 channel E0UC[22] or FlexCAN_3 transmitter; medium slew rate output buffer."+ },+ {+ "number": "14",+ "name": "PE[9]",+ "type": "input",+ "description": "GPIO[73] or eMIOS_0 channel E0UC[23] or wakeup input WKPU[7] or FlexCAN_2/3 receiver; Schmitt trigger input."+ },+ {+ "number": "15",+ "name": "PE[10]",+ "type": "bidirectional",+ "description": "GPIO[74] or LINFlex_3 transmitter or DSPI_1 chip select; slow slew rate output buffer."+ },+ {+ "number": "16",+ "name": "PA[0]",+ "type": "bidirectional",+ "description": "GPIO[0] or eMIOS_0 channel E0UC[0] or system clock output or wakeup input WKPU[19]; medium slew rate output buffer."+ },+ {+ "number": "17",+ "name": "PE[11]",+ "type": "bidirectional",+ "description": "GPIO[75] or DSPI_1 chip select CS4_1 or LINFlex_3 receiver or wakeup input WKPU[14]; slow slew rate output buffer."+ },+ {+ "number": "18",+ "name": "VSS_HV",+ "type": "power_in",+ "description": "Digital ground reference for high-voltage domain VDD_HV power supply."+ },+ {+ "number": "19",+ "name": "VDD_HV",+ "type": "power_in",+ "description": "Digital supply voltage (3.3V or 5.0V nominal); 100nF ceramic capacitor required between VDD_HV and nearest VSS_HV pin."+ },+ {+ "number": "20",+ "name": "VSS_HV",+ "type": "power_in",+ "description": "Digital ground reference for high-voltage domain VDD_HV power supply."+ },+ {+ "number": "21",+ "name": "RESET",+ "type": "bidirectional",+ "description": "Bidirectional reset pin with Schmitt trigger and integrated noise filter for 1µs glitch rejection; requires external pull-up resistor."+ },+ {+ "number": "22",+ "name": "VSS_LV",+ "type": "power_in",+ "description": "Low-voltage (1.2V) domain ground; 330nF ceramic capacitor required between nearest VDD_LV pin and this pin for regulator stability."+ },+ {+ "number": "23",+ "name": "VDD_LV",+ "type": "power_in",+ "description": "Low-voltage (1.2V) internal regulator output; 330nF ceramic capacitor required between this pin and nearest VSS_LV pin for regulator stability."+ },+ {+ "number": "24",+ "name": "VDD_BV",+ "type": "power_in",+ "description": "Internal voltage regulator ballast supply voltage (3.3V or 5.0V aligned with VDD); 100nF to 470nF decoupling capacitor required."+ },+ {+ "number": "25",+ "name": "PG[9]",+ "type": "bidirectional",+ "description": "GPIO[105] or eMIOS_1 channel E1UC[18] or DSPI_2 serial clock; slow slew rate output buffer."+ },+ {+ "number": "26",+ "name": "PG[8]",+ "type": "bidirectional",+ "description": "GPIO[104] or eMIOS_1 channel E1UC[17] or DSPI_2 chip select or external interrupt EIRQ[15]; slow slew rate output buffer."+ },+ {+ "number": "27",+ "name": "PC[11]",+ "type": "input",+ "description": "GPIO[43] or FlexCAN_1 receiver or FlexCAN_4 receiver or wakeup input WKPU[5]; Schmitt trigger input."+ },+ {+ "number": "28",+ "name": "PC[10]",+ "type": "bidirectional",+ "description": "GPIO[42] or FlexCAN_1 transmitter or FlexCAN_4 transmitter or ADC multiplexer control MA[1]; medium slew rate output buffer."+ },+ {+ "number": "29",+ "name": "PG[7]",+ "type": "bidirectional",+ "description": "GPIO[103] or eMIOS_1 channel E1UC[16]; medium slew rate output buffer."+ },+ {+ "number": "30",+ "name": "PG[6]",+ "type": "bidirectional",+ "description": "GPIO[102] or eMIOS_1 channel E1UC[15]; medium slew rate output buffer."+ },+ {+ "number": "31",+ "name": "PB[0]",+ "type": "bidirectional",+ "description": "GPIO[16] or FlexCAN_0 transmitter; medium slew rate output buffer."+ },+ {+ "number": "32",+ "name": "PB[1]",+ "type": "input",+ "description": "GPIO[17] or FlexCAN_0 receiver or wakeup input WKPU[4]; Schmitt trigger input."+ },+ {+ "number": "33",+ "name": "PF[9]",+ "type": "bidirectional",+ "description": "GPIO[89] or DSPI_0 chip select CS5_0 or FlexCAN_2/3 receiver; slow slew rate output buffer."+ },+ {+ "number": "34",+ "name": "PF[8]",+ "type": "bidirectional",+ "description": "GPIO[88] or FlexCAN_3 transmitter or DSPI_0 chip select CS4_0 or FlexCAN_2 transmitter; medium slew rate output buffer."+ },+ {+ "number": "35",+ "name": "PF[12]",+ "type": "bidirectional",+ "description": "GPIO[92] or eMIOS_1 channel E1UC[25]; medium slew rate output buffer."+ },+ {+ "number": "36",+ "name": "PC[6]",+ "type": "bidirectional",+ "description": "GPIO[38] or LINFlex_1 transmitter; slow slew rate output buffer."+ },+ {+ "number": "37",+ "name": "PC[7]",+ "type": "input",+ "description": "GPIO[39] or LINFlex_1 receiver or wakeup input WKPU[12]; Schmitt trigger input."+ },+ {+ "number": "38",+ "name": "PF[10]",+ "type": "bidirectional",+ "description": "GPIO[90]; medium slew rate output buffer."+ },+ {+ "number": "39",+ "name": "PF[11]",+ "type": "input",+ "description": "GPIO[91] or wakeup input WKPU[15]; Schmitt trigger input."+ },+ {+ "number": "40",+ "name": "PA[15]",+ "type": "bidirectional",+ "description": "GPIO[15] or DSPI_0 chip select CS0_0 or serial clock SCK_0 or wakeup input WKPU[10]; medium slew rate output buffer."+ },+ {+ "number": "41",+ "name": "PF[13]",+ "type": "input",+ "description": "GPIO[93] or eMIOS_1 channel E1UC[26] or wakeup input WKPU[16]; Schmitt trigger input."+ },+ {+ "number": "42",+ "name": "PA[14]",+ "type": "bidirectional",+ "description": "GPIO[14] or DSPI_0 serial clock SCK_0 or chip select CS0_0 or external interrupt EIRQ[4]; medium slew rate output buffer."+ },+ {+ "number": "43",+ "name": "PA[4]",+ "type": "input",+ "description": "GPIO[4] or eMIOS_0 channel E0UC[4] or wakeup input WKPU[9]; Schmitt trigger input."+ },+ {+ "number": "44",+ "name": "PA[13]",+ "type": "bidirectional",+ "description": "GPIO[13] or DSPI_0 serial data output; medium slew rate output buffer."+ },+ {+ "number": "45",+ "name": "PA[12]",+ "type": "input",+ "description": "GPIO[12] or DSPI_0 serial data input; Schmitt trigger input."+ },+ {+ "number": "46",+ "name": "VDD_LV",+ "type": "power_in",+ "description": "Low-voltage (1.2V) internal regulator output; 330nF ceramic capacitor required between this pin and nearest VSS_LV pin for regulator stability."+ },+ {+ "number": "47",+ "name": "VSS_LV",+ "type": "power_in",+ "description": "Low-voltage (1.2V) domain ground; 330nF ceramic capacitor required between nearest VDD_LV pin and this pin for regulator stability."+ },+ {+ "number": "48",+ "name": "XTAL",+ "type": "bidirectional",+ "description": "External crystal oscillator input requiring connection to ground if oscillator is operated in bypass mode; part of 4-16MHz crystal oscillator circuit."+ },+ {+ "number": "49",+ "name": "VSS_HV",+ "type": "power_in",+ "description": "Digital ground reference for high-voltage domain VDD_HV power supply."+ },+ {+ "number": "50",+ "name": "EXTAL",+ "type": "bidirectional",+ "description": "External crystal oscillator amplifier output in normal oscillator mode or analog clock input in bypass mode; part of 4-16MHz crystal oscillator circuit."+ },+ {+ "number": "51",+ "name": "VDD_HV",+ "type": "power_in",+ "description": "Digital supply voltage (3.3V or 5.0V nominal); 100nF ceramic capacitor required between VDD_HV and nearest VSS_HV pin."+ },+ {+ "number": "52",+ "name": "PB[9]",+ "type": "bidirectional",+ "description": "GPIO[25] or 32kHz slow external crystal oscillator EXTAL or ADC channel ANS[1]; fast input-only analog pad."+ },+ {+ "number": "53",+ "name": "PB[8]",+ "type": "bidirectional",+ "description": "GPIO[24] or 32kHz slow external crystal oscillator XTAL or ADC channel ANS[0]; fast input-only analog pad."+ },+ {+ "number": "54",+ "name": "PB[10]",+ "type": "bidirectional",+ "description": "GPIO[26] or ADC channel ANS[2] or wakeup input WKPU[8]; J-type pad with analog feature."+ },+ {+ "number": "55",+ "name": "PF[0]",+ "type": "bidirectional",+ "description": "GPIO[80] or eMIOS_0 channel E0UC[10] or DSPI_1 chip select CS3_0 or ADC channel ANS[8]; J-type pad with analog feature."+ },+ {+ "number": "56",+ "name": "PF[1]",+ "type": "bidirectional",+ "description": "GPIO[81] or eMIOS_0 channel E0UC[11] or DSPI_1 chip select CS4_0 or ADC channel ANS[9]; J-type pad with analog feature."+ },+ {+ "number": "57",+ "name": "PF[2]",+ "type": "bidirectional",+ "description": "GPIO[82] or eMIOS_0 channel E0UC[12] or DSPI_2 chip select CS0_2 or ADC channel ANS[10]; J-type pad with analog feature."+ },+ {+ "number": "58",+ "name": "PF[3]",+ "type": "bidirectional",+ "description": "GPIO[83] or eMIOS_0 channel E0UC[13] or DSPI_2 chip select CS1_2 or ADC channel ANS[11]; J-type pad with analog feature."+ },+ {+ "number": "59",+ "name": "PF[4]",+ "type": "bidirectional",+ "description": "GPIO[84] or eMIOS_0 channel E0UC[14] or DSPI_2 chip select CS2_2 or ADC channel ANS[12]; J-type pad with analog feature."+ },+ {+ "number": "60",+ "name": "PF[5]",+ "type": "bidirectional",+ "description": "GPIO[85] or eMIOS_0 channel E0UC[22] or DSPI_2 chip select CS3_2 or ADC channel ANS[13]; J-type pad with analog feature."+ },+ {+ "number": "61",+ "name": "PF[6]",+ "type": "bidirectional",+ "description": "GPIO[86] or eMIOS_0 channel E0UC[23] or ADC channel ANS[14]; J-type pad with analog feature."+ },+ {+ "number": "62",+ "name": "PF[7]",+ "type": "bidirectional",+ "description": "GPIO[87] or ADC channel ANS[15]; J-type pad with analog feature."+ },+ {+ "number": "63",+ "name": "PD[0]",+ "type": "input",+ "description": "GPIO[48] or ADC precise channel GPI[4]; fast input-only pad without output buffer."+ },+ {+ "number": "64",+ "name": "PD[1]",+ "type": "input",+ "description": "GPIO[49] or ADC precise channel GPI[5]; fast input-only pad without output buffer."+ },+ {+ "number": "65",+ "name": "PD[2]",+ "type": "input",+ "description": "GPIO[50] or ADC precise channel GPI[6]; fast input-only pad without output buffer."+ },+ {+ "number": "66",+ "name": "PD[3]",+ "type": "input",+ "description": "GPIO[51] or ADC precise channel GPI[7]; fast input-only pad without output buffer."+ },+ {+ "number": "67",+ "name": "PD[4]",+ "type": "input",+ "description": "GPIO[52] or ADC precise channel GPI[8]; fast input-only pad without output buffer."+ },+ {+ "number": "68",+ "name": "PD[5]",+ "type": "input",+ "description": "GPIO[53] or ADC precise channel GPI[9]; fast input-only pad without output buffer."+ },+ {+ "number": "69",+ "name": "PD[6]",+ "type": "input",+ "description": "GPIO[54] or ADC precise channel GPI[10]; fast input-only pad without output buffer."+ },+ {+ "number": "70",+ "name": "PD[7]",+ "type": "input",+ "description": "GPIO[55] or ADC precise channel GPI[11]; fast input-only pad without output buffer."+ },+ {+ "number": "71",+ "name": "PD[8]",+ "type": "input",+ "description": "GPIO[56] or ADC precise channel GPI[12]; fast input-only pad without output buffer."+ },+ {+ "number": "72",+ "name": "PB[4]",+ "type": "input",+ "description": "GPIO[20] or ADC precise channel GPI[0]; fast input-only pad without output buffer."+ },+ {+ "number": "73",+ "name": "VSS_HV_ADC",+ "type": "power_in",+ "description": "ADC reference ground and analog ground; must be connected to VSS_HV externally to ensure common ground."+ },+ {+ "number": "74",+ "name": "VDD_HV_ADC",+ "type": "power_in",+ "description": "ADC reference voltage supply; 1µF electrolytic + 47nF ceramic capacitor required between VDD_HV_ADC and VSS_HV_ADC for ADC accuracy."+ },+ {+ "number": "75",+ "name": "PB[5]",+ "type": "input",+ "description": "GPIO[21] or ADC precise channel GPI[1]; fast input-only pad without output buffer."+ },+ {+ "number": "76",+ "name": "PB[6]",+ "type": "input",+ "description": "GPIO[22] or ADC precise channel GPI[2]; fast input-only pad without output buffer."+ },+ {+ "number": "77",+ "name": "PB[7]",+ "type": "input",+ "description": "GPIO[23] or ADC precise channel GPI[3]; fast input-only pad without output buffer."+ },+ {+ "number": "78",+ "name": "PD[9]",+ "type": "input",+ "description": "GPIO[57] or ADC precise channel GPI[13]; fast input-only pad without output buffer."+ },+ {+ "number": "79",+ "name": "PD[10]",+ "type": "input",+ "description": "GPIO[58] or ADC precise channel GPI[14]; fast input-only pad without output buffer."+ },+ {+ "number": "80",+ "name": "PD[11]",+ "type": "input",+ "description": "GPIO[59] or ADC precise channel GPI[15]; fast input-only pad without output buffer."+ },+ {+ "number": "81",+ "name": "PB[11]",+ "type": "bidirectional",+ "description": "GPIO[27] or eMIOS_0 channel E0UC[3] or DSPI_0 chip select CS0_0 or ADC channel ANS[3]; J-type pad with analog feature."+ },+ {+ "number": "82",+ "name": "PD[12]",+ "type": "bidirectional",+ "description": "GPIO[60] or DSPI_0 chip select CS5_0 or eMIOS_0 channel E0UC[24] or ADC channel ANS[4]; J-type pad with analog feature."+ },+ {+ "number": "83",+ "name": "PB[12]",+ "type": "bidirectional",+ "description": "GPIO[28] or eMIOS_0 channel E0UC[4] or DSPI_0 chip select CS1_0 or ADC extended channel ANX[0]; J-type pad with analog feature."+ },+ {+ "number": "84",+ "name": "PD[13]",+ "type": "bidirectional",+ "description": "GPIO[61] or DSPI_1 chip select CS0_1 or eMIOS_0 channel E0UC[25] or ADC channel ANS[5]; J-type pad with analog feature."+ },+ {+ "number": "85",+ "name": "PB[13]",+ "type": "bidirectional",+ "description": "GPIO[29] or eMIOS_0 channel E0UC[5] or DSPI_0 chip select CS2_0 or ADC extended channel ANX[1]; J-type pad with analog feature."+ },+ {+ "number": "86",+ "name": "PD[14]",+ "type": "bidirectional",+ "description": "GPIO[62] or DSPI_1 chip select CS1_1 or eMIOS_0 channel E0UC[26] or ADC channel ANS[6]; J-type pad with analog feature."+ },+ {+ "number": "87",+ "name": "PB[14]",+ "type": "bidirectional",+ "description": "GPIO[30] or eMIOS_0 channel E0UC[6] or DSPI_0 chip select CS3_0 or ADC extended channel ANX[2]; J-type pad with analog feature."+ },+ {+ "number": "88",+ "name": "PD[15]",+ "type": "bidirectional",+ "description": "GPIO[63] or DSPI_1 chip select CS2_1 or eMIOS_0 channel E0UC[27] or ADC channel ANS[7]; J-type pad with analog feature."+ },+ {+ "number": "89",+ "name": "PB[15]",+ "type": "bidirectional",+ "description": "GPIO[31] or eMIOS_0 channel E0UC[7] or DSPI_0 chip select CS4_0 or ADC extended channel ANX[3]; J-type pad with analog feature."+ },+ {+ "number": "90",+ "name": "PA[3]",+ "type": "input",+ "description": "GPIO[3] or eMIOS_0 channel E0UC[3] or external interrupt EIRQ[0]; Schmitt trigger input."+ },+ {+ "number": "91",+ "name": "PG[13]",+ "type": "bidirectional",+ "description": "GPIO[109] or eMIOS_0 channel E0UC[27]; medium slew rate output buffer."+ },+ {+ "number": "92",+ "name": "PG[12]",+ "type": "bidirectional",+ "description": "GPIO[108] or eMIOS_0 channel E0UC[26]; medium slew rate output buffer."+ },+ {+ "number": "93",+ "name": "PH[0]",+ "type": "bidirectional",+ "description": "GPIO[112] or eMIOS_1 channel E1UC[2] or DSPI_1 serial data input; medium slew rate output buffer."+ },+ {+ "number": "94",+ "name": "PH[1]",+ "type": "bidirectional",+ "description": "GPIO[113] or eMIOS_1 channel E1UC[3] or DSPI_1 serial data output; medium slew rate output buffer."+ },+ {+ "number": "95",+ "name": "PH[2]",+ "type": "bidirectional",+ "description": "GPIO[114] or eMIOS_1 channel E1UC[4] or DSPI_1 serial clock; medium slew rate output buffer."+ },+ {+ "number": "96",+ "name": "PH[3]",+ "type": "bidirectional",+ "description": "GPIO[115] or eMIOS_1 channel E1UC[5] or DSPI_1 chip select CS0_1; medium slew rate output buffer."+ },+ {+ "number": "97",+ "name": "PG[1]",+ "type": "input",+ "description": "GPIO[97] or eMIOS_1 channel E1UC[24] or FlexCAN_5 receiver or external interrupt EIRQ[14]; Schmitt trigger input."+ },+ {+ "number": "98",+ "name": "PG[0]",+ "type": "bidirectional",+ "description": "GPIO[96] or FlexCAN_5 transmitter or eMIOS_1 channel E1UC[23]; medium slew rate output buffer."+ },+ {+ "number": "99",+ "name": "VSS_HV",+ "type": "power_in",+ "description": "Digital ground reference for high-voltage domain VDD_HV power supply."+ },+ {+ "number": "100",+ "name": "VDD_HV",+ "type": "power_in",+ "description": "Digital supply voltage (3.3V or 5.0V nominal); 100nF ceramic capacitor required between VDD_HV and nearest VSS_HV pin."+ },+ {+ "number": "101",+ "name": "PF[15]",+ "type": "input",+ "description": "GPIO[95] or FlexCAN_1 receiver or FlexCAN_4 receiver or external interrupt EIRQ[13]; Schmitt trigger input."+ },+ {+ "number": "102",+ "name": "PF[14]",+ "type": "bidirectional",+ "description": "GPIO[94] or FlexCAN_4 transmitter or eMIOS_1 channel E1UC[27] or FlexCAN_1 transmitter; medium slew rate output buffer."+ },+ {+ "number": "103",+ "name": "PE[13]",+ "type": "bidirectional",+ "description": "GPIO[77] or DSPI_2 serial data output or eMIOS_1 channel E1UC[20]; slow slew rate output buffer."+ },+ {+ "number": "104",+ "name": "PA[7]",+ "type": "bidirectional",+ "description": "GPIO[7] or eMIOS_0 channel E0UC[7] or LINFlex_3 transmitter or external interrupt EIRQ[2]; slow slew rate output buffer."+ },+ {+ "number": "105",+ "name": "PA[8]",+ "type": "bidirectional",+ "description": "GPIO[8] or eMIOS_0 channel E0UC[8] or external interrupt EIRQ[3] or boot mode FAB pin or LINFlex_3 receiver; weak pull-up after reset."+ },+ {+ "number": "106",+ "name": "PA[9]",+ "type": "bidirectional",+ "description": "GPIO[9] or eMIOS_0 channel E0UC[9] or boot mode FAB pin (pull-down during reset); slow slew rate output buffer."+ },+ {+ "number": "107",+ "name": "PA[10]",+ "type": "bidirectional",+ "description": "GPIO[10] or eMIOS_0 channel E0UC[10] or I2C_0 SDA (open-drain); slow slew rate output buffer."+ },+ {+ "number": "108",+ "name": "PA[11]",+ "type": "bidirectional",+ "description": "GPIO[11] or eMIOS_0 channel E0UC[11] or I2C_0 SCL (open-drain); slow slew rate output buffer."+ },+ {+ "number": "109",+ "name": "PE[12]",+ "type": "bidirectional",+ "description": "GPIO[76] or DSPI_2 serial data input or external interrupt EIRQ[11]; medium slew rate output buffer."+ },+ {+ "number": "110",+ "name": "PG[14]",+ "type": "bidirectional",+ "description": "GPIO[110] or eMIOS_1 channel E1UC[0]; slow slew rate output buffer."+ },+ {+ "number": "111",+ "name": "PG[15]",+ "type": "bidirectional",+ "description": "GPIO[111] or eMIOS_1 channel E1UC[1]; medium slew rate output buffer."+ },+ {+ "number": "112",+ "name": "PE[14]",+ "type": "bidirectional",+ "description": "GPIO[78] or DSPI_2 serial clock or eMIOS_1 channel E1UC[21] or external interrupt EIRQ[12]; slow slew rate output buffer."+ },+ {+ "number": "113",+ "name": "PE[15]",+ "type": "bidirectional",+ "description": "GPIO[79] or DSPI_2 chip select CS0_2 or eMIOS_1 channel E1UC[22]; medium slew rate output buffer."+ },+ {+ "number": "114",+ "name": "PG[10]",+ "type": "bidirectional",+ "description": "GPIO[106] or eMIOS_0 channel E0UC[24]; slow slew rate output buffer."+ },+ {+ "number": "115",+ "name": "PG[11]",+ "type": "bidirectional",+ "description": "GPIO[107] or eMIOS_0 channel E0UC[25]; medium slew rate output buffer."+ },+ {+ "number": "116",+ "name": "PC[3]",+ "type": "bidirectional",+ "description": "GPIO[35] or DSPI_1 chip select CS0_1 or ADC multiplexer MA[0] or FlexCAN_1 receiver or FlexCAN_4 receiver or external interrupt EIRQ[6]; slow slew rate output buffer."+ },+ {+ "number": "117",+ "name": "PC[2]",+ "type": "bidirectional",+ "description": "GPIO[34] or DSPI_1 serial clock or FlexCAN_4 transmitter or external interrupt EIRQ[5]; medium slew rate output buffer."+ },+ {+ "number": "118",+ "name": "PA[5]",+ "type": "bidirectional",+ "description": "GPIO[5] or eMIOS_0 channel E0UC[5]; medium slew rate output buffer."+ },+ {+ "number": "119",+ "name": "PA[6]",+ "type": "input",+ "description": "GPIO[6] or eMIOS_0 channel E0UC[6] or external interrupt EIRQ[1]; Schmitt trigger input."+ },+ {+ "number": "120",+ "name": "PH[10]",+ "type": "bidirectional",+ "description": "GPIO[122] or JTAG test mode select (TMS); weak pull-up input, slow slew rate output buffer."+ },+ {+ "number": "121",+ "name": "PC[1]",+ "type": "bidirectional",+ "description": "GPIO[33] or JTAG test data output (TDO); external pull-up required in STANDBY mode, medium slew rate output buffer."+ },+ {+ "number": "122",+ "name": "VSS_HV",+ "type": "power_in",+ "description": "Digital ground reference for high-voltage domain VDD_HV power supply."+ },+ {+ "number": "123",+ "name": "VDD_HV",+ "type": "power_in",+ "description": "Digital supply voltage (3.3V or 5.0V nominal); 100nF ceramic capacitor required between VDD_HV and nearest VSS_HV pin."+ },+ {+ "number": "124",+ "name": "VDD_LV",+ "type": "power_in",+ "description": "Low-voltage (1.2V) internal regulator output; 330nF ceramic capacitor required between this pin and nearest VSS_LV pin for regulator stability."+ },+ {+ "number": "125",+ "name": "VSS_LV",+ "type": "power_in",+ "description": "Low-voltage (1.2V) domain ground; 330nF ceramic capacitor required between nearest VDD_LV pin and this pin for regulator stability."+ },+ {+ "number": "126",+ "name": "PC[0]",+ "type": "bidirectional",+ "description": "GPIO[32] or JTAG test data input (TDI); weak pull-up input, medium slew rate output buffer."+ },+ {+ "number": "127",+ "name": "PH[9]",+ "type": "bidirectional",+ "description": "GPIO[121] or JTAG test clock input (TCK); weak pull-up input, slow slew rate output buffer."+ },+ {+ "number": "128",+ "name": "PE[2]",+ "type": "bidirectional",+ "description": "GPIO[66] or eMIOS_0 channel E0UC[18] or DSPI_1 serial data input; medium slew rate output buffer."+ },+ {+ "number": "129",+ "name": "PE[3]",+ "type": "bidirectional",+ "description": "GPIO[67] or eMIOS_0 channel E0UC[19] or DSPI_1 serial data output; medium slew rate output buffer."+ },+ {+ "number": "130",+ "name": "PC[5]",+ "type": "bidirectional",+ "description": "GPIO[37] or DSPI_1 serial data output or FlexCAN_3 transmitter or external interrupt EIRQ[7]; medium slew rate output buffer."+ },+ {+ "number": "131",+ "name": "PC[4]",+ "type": "bidirectional",+ "description": "GPIO[36] or DSPI_1 serial data input or FlexCAN_3 receiver; medium slew rate output buffer."+ },+ {+ "number": "132",+ "name": "PE[4]",+ "type": "bidirectional",+ "description": "GPIO[68] or eMIOS_0 channel E0UC[20] or DSPI_1 serial clock or external interrupt EIRQ[9]; medium slew rate output buffer."+ },+ {+ "number": "133",+ "name": "PE[5]",+ "type": "bidirectional",+ "description": "GPIO[69] or eMIOS_0 channel E0UC[21] or DSPI_1 chip select CS0_1 or ADC multiplexer MA[2]; medium slew rate output buffer."+ },+ {+ "number": "134",+ "name": "PH[4]",+ "type": "bidirectional",+ "description": "GPIO[116] or eMIOS_1 channel E1UC[6]; medium slew rate output buffer."+ },+ {+ "number": "135",+ "name": "PH[5]",+ "type": "bidirectional",+ "description": "GPIO[117] or eMIOS_1 channel E1UC[7]; slow slew rate output buffer."+ },+ {+ "number": "136",+ "name": "PH[6]",+ "type": "bidirectional",+ "description": "GPIO[118] or eMIOS_1 channel E1UC[8] or ADC multiplexer MA[2]; medium slew rate output buffer."+ },+ {+ "number": "137",+ "name": "PH[7]",+ "type": "bidirectional",+ "description": "GPIO[119] or eMIOS_1 channel E1UC[9] or DSPI_2 chip select CS3_2 or ADC multiplexer MA[1]; medium slew rate output buffer."+ },+ {+ "number": "138",+ "name": "PH[8]",+ "type": "bidirectional",+ "description": "GPIO[120] or eMIOS_1 channel E1UC[10] or DSPI_2 chip select CS2_2 or ADC multiplexer MA[0]; medium slew rate output buffer."+ },+ {+ "number": "139",+ "name": "PE[6]",+ "type": "bidirectional",+ "description": "GPIO[70] or eMIOS_0 channel E0UC[22] or DSPI_0 chip select CS3_0 or ADC multiplexer MA[1]; medium slew rate output buffer."+ },+ {+ "number": "140",+ "name": "PE[7]",+ "type": "bidirectional",+ "description": "GPIO[71] or eMIOS_0 channel E0UC[23] or DSPI_0 chip select CS2_0 or ADC multiplexer MA[0]; medium slew rate output buffer."+ },+ {+ "number": "141",+ "name": "PC[12]",+ "type": "bidirectional",+ "description": "GPIO[44] or eMIOS_0 channel E0UC[12] or DSPI_2 serial data input; medium slew rate output buffer."+ },+ {+ "number": "142",+ "name": "PC[13]",+ "type": "bidirectional",+ "description": "GPIO[45] or eMIOS_0 channel E0UC[13] or DSPI_2 serial data output; slow slew rate output buffer."+ },+ {+ "number": "143",+ "name": "PC[8]",+ "type": "bidirectional",+ "description": "GPIO[40] or LINFlex_2 transmitter; slow slew rate output buffer."+ },+ {+ "number": "144",+ "name": "PB[2]",+ "type": "bidirectional",+ "description": "GPIO[18] or LINFlex_0 transmitter or I2C_0 SDA (open-drain); medium slew rate output buffer."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: LQFP64 package information in datasheet is marked as 'indicative and must be confirmed during silico; Some ADC pins (PD[0-11], PB[4-7]) are marked as precise input-only channels without GPIO capability ; DSPI pins have multiple alternate functions (input vs output) depending on master/slave mode configu"+ ],+ "pages_sent": null,+ "cost_usd": 0.5294,+ "at": "2026-09-30T01:48:09"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8584346429225095168",+ "pages": 116,+ "sha256": "17b37543a9b5ee31",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 144,+ "described": 144,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}