SP706REN-L

@@ -0,0 +1,48 @@+# SP706REN-L++**MaxLinear** · Supervisor and Reset ICs · SOIC-8++SP706REN-L from MaxLinear, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | MR | input | Manual Reset input, active LOW. Triggers a reset pulse when pulled below 0.8V. Has an internal 70µA (typ) pull-up current, so it can be driven by a TTL/CMOS logic line or shorted to ground with a switch. Debounced. |+| 2 | VCC | power_in | Supply voltage input. Operating range 2.7V to 5.5V for SP706R. Absolute maximum 6.0V. Bypass with 100nF close to the pin for transient immunity. |+| 3 | GND | power_in | Ground reference for all signals. |+| 4 | PFI | input | Power-Fail comparator Input. When this voltage-monitor input falls below the 1.25V (typ) threshold, the PFO output goes LOW. Typically driven from a resistor divider from the monitored rail. Connect PFI to GND or VCC when the feature is unused. |+| 5 | PFO | output | Power-Fail comparator Output. HIGH while PFI is above 1.25V; drives LOW when PFI drops below 1.25V. Push-pull CMOS output. |+| 6 | WDI | input | Watchdog Input. If WDI stays HIGH or LOW for the 1.6s watchdog timeout, WDO goes LOW. Every rising or falling edge on WDI clears the internal watchdog timer. Floating the pin (or driving from a high-impedance tri-state buffer) disables the watchdog. The timer also clears whenever RESET is asserted. |+| 7 | RESET | output | Active-LOW RESET output. Pulses LOW for 200ms (typ) when triggered and remains LOW whenever VCC is below the reset threshold (2.63V typ). Stays LOW for 200ms after VCC rises above threshold or MR goes LOW-to-HIGH. Guaranteed valid down to VCC = 1V. A watchdog timeout alone does not assert RESET unless WDO is externally tied to MR. |+| 8 | WDO | output | Watchdog Output. Drives LOW when the internal 1.6s watchdog timer expires and stays LOW until the watchdog is cleared. Also held LOW while VCC is below the reset threshold; unlike RESET, WDO has no minimum pulse width and returns HIGH with no delay once VCC recovers. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | MaxLinear |+| Package | SOIC-8 |+| Category | PMIC |+| Pins | 8 |++## Ordering variants++- `SP706REN-LRCN-L/TR`+- `SP706REN-LREN-L/TR`++## CAD (KiCad official)++- Symbol: `SP706REN-L`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [MaxLinear datasheet](docs/sp706ren-l-datasheet.pdf) (22 pp, sha256 `1fdc9a48adbd252a`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sp706ren-l-datasheet.pdf)

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