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Initial commit: component/sn74lvu04apwr

Ray ·83d490429b ·10d ago
2 files changed +241
README.mdadded+50
@@ -0,0 +1,50 @@+# SN74LVU04APWR++**Texas Instruments** · Inverters · TSSOP-14++SN74LVU04APWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Input to inverter 1; accepts 0 V to 5.5 V logic levels. |+| 2 | 1Y | output | Output of inverter 1; provides inverted logic output to VCC or 0 V. |+| 3 | 2A | input | Input to inverter 2; accepts 0 V to 5.5 V logic levels. |+| 4 | 2Y | output | Output of inverter 2; provides inverted logic output to VCC or 0 V. |+| 5 | 3A | input | Input to inverter 3; accepts 0 V to 5.5 V logic levels. |+| 6 | 3Y | output | Output of inverter 3; provides inverted logic output to VCC or 0 V. |+| 7 | GND | power_in | Ground (0 V) reference; maximum continuous current ±50 mA. |+| 8 | 4Y | output | Output of inverter 4; provides inverted logic output to VCC or 0 V. |+| 9 | 4A | input | Input to inverter 4; accepts 0 V to 5.5 V logic levels. |+| 10 | 5Y | output | Output of inverter 5; provides inverted logic output to VCC or 0 V. |+| 11 | 5A | input | Input to inverter 5; accepts 0 V to 5.5 V logic levels. |+| 12 | 6Y | output | Output of inverter 6; provides inverted logic output to VCC or 0 V. |+| 13 | 6A | input | Input to inverter 6; accepts 0 V to 5.5 V logic levels. |+| 14 | VCC | power_in | Positive supply voltage 2 V to 5.5 V; maximum continuous current ±50 mA. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74LVU04APWR`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `sn74lvu04apwr-etched.step` / `sn74lvu04apwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvu04apwr.step` / `sn74lvu04apwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvu04a.pdf) (20 pp, sha256 `ce5ba0b9543ad963`, retrieved 2026-09-25, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvu04apwr-datasheet.pdf)
page.jsonadded+191
@@ -0,0 +1,191 @@+{+  "slug": "sn74lvu04apwr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Inverters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "sn74lvu04apwr",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "sn74lvu04apwr.kicad_sym",+    "sn74lvu04apwr.kicad_mod",+    "sn74lvu04apwr.glb",+    "sn74lvu04apwr.step",+    "sn74lvu04apwr.lbr",+    "docs/hero.png",+    "docs/sn74lvu04apwr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "SN74LVU04APWR",+    "manufacturer": "Texas Instruments",+    "package": "TSSOP-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Inverters",+    "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvu04a.pdf",+    "parts": {+      "symbol": "sn74lvu04apwr.kicad_sym",+      "footprint": "sn74lvu04apwr.kicad_mod",+      "model_3d": "sn74lvu04apwr-etched.glb",+      "model_3d_plain": "sn74lvu04apwr.glb",+      "model_3d_step": "sn74lvu04apwr-etched.step",+      "model_3d_step_plain": "sn74lvu04apwr.step",+      "lbr": "sn74lvu04apwr.lbr"+    },+    "distributor_links": {+      "lcsc": "C2870631",+      "digikey": "296-9885-2-ND",+      "mouser": "595-SN74LVU04APWR"+    },+    "distributor_check": {+      "checked_at": "2026-09-25T14:07:05Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": "296-9885-2-ND",+        "status": "found"+      },+      "mouser": {+        "pn": "595-SN74LVU04APWR",+        "status": "found"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "1A",+        "type": "input",+        "description": "Input to inverter 1; accepts 0 V to 5.5 V logic levels."+      },+      {+        "number": "2",+        "name": "1Y",+        "type": "output",+        "description": "Output of inverter 1; provides inverted logic output to VCC or 0 V."+      },+      {+        "number": "3",+        "name": "2A",+        "type": "input",+        "description": "Input to inverter 2; accepts 0 V to 5.5 V logic levels."+      },+      {+        "number": "4",+        "name": "2Y",+        "type": "output",+        "description": "Output of inverter 2; provides inverted logic output to VCC or 0 V."+      },+      {+        "number": "5",+        "name": "3A",+        "type": "input",+        "description": "Input to inverter 3; accepts 0 V to 5.5 V logic levels."+      },+      {+        "number": "6",+        "name": "3Y",+        "type": "output",+        "description": "Output of inverter 3; provides inverted logic output to VCC or 0 V."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground (0 V) reference; maximum continuous current ±50 mA."+      },+      {+        "number": "8",+        "name": "4Y",+        "type": "output",+        "description": "Output of inverter 4; provides inverted logic output to VCC or 0 V."+      },+      {+        "number": "9",+        "name": "4A",+        "type": "input",+        "description": "Input to inverter 4; accepts 0 V to 5.5 V logic levels."+      },+      {+        "number": "10",+        "name": "5Y",+        "type": "output",+        "description": "Output of inverter 5; provides inverted logic output to VCC or 0 V."+      },+      {+        "number": "11",+        "name": "5A",+        "type": "input",+        "description": "Input to inverter 5; accepts 0 V to 5.5 V logic levels."+      },+      {+        "number": "12",+        "name": "6Y",+        "type": "output",+        "description": "Output of inverter 6; provides inverted logic output to VCC or 0 V."+      },+      {+        "number": "13",+        "name": "6A",+        "type": "input",+        "description": "Input to inverter 6; accepts 0 V to 5.5 V logic levels."+      },+      {+        "number": "14",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply voltage 2 V to 5.5 V; maximum continuous current ±50 mA."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 20,+        "cost_usd": 0.1869,+        "at": "2026-09-25T14:06:43"+      },+      "datasheet": {+        "url": "https://www.ti.com/lit/ds/symlink/sn74lvu04a.pdf",+        "pages": 20,+        "sha256": "ce5ba0b9543ad963",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file