SN74LVTH125PWR

@@ -0,0 +1,63 @@+# SN74LVTH125PWR++**Texas Instruments** · Buffer/Driver/Transceiver · TSSOP-14++SN74LVTH125PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1OE | input | Active-low output-enable for buffer 1. Drive low to enable the 1Y output; drive high to place 1Y in the high-impedance state. Bus-hold circuitry does NOT act on control inputs, so this pin must be actively driven or tied to VCC/GND. |+| 2 | 1A | input | Data input for buffer 1. TTL-compatible input accepting 0 to 5.5 V. Includes bus-hold circuitry that keeps an undriven input at its last valid logic level, so external pull-up/pull-down resistors are not required. |+| 3 | 1Y | tri_state | 3-state buffered output for channel 1. Follows 1A when 1OE is low; goes to high-impedance when 1OE is high. Drive strength: IOH = -32 mA, IOL = 64 mA (commercial temperature grade). |+| 4 | 2OE | input | Active-low output-enable for buffer 2. Drive low to enable the 2Y output; drive high to place 2Y in the high-impedance state. |+| 5 | 2A | input | Data input for buffer 2. TTL-compatible input accepting 0 to 5.5 V. Includes bus-hold on the input. |+| 6 | 2Y | tri_state | 3-state buffered output for channel 2. Follows 2A when 2OE is low; high-impedance when 2OE is high. |+| 7 | GND | power_in | Device ground reference (0 V). Connect to the system ground plane with a low-inductance path. |+| 8 | 3Y | tri_state | 3-state buffered output for channel 3. Follows 3A when 3OE is low; high-impedance when 3OE is high. |+| 9 | 3A | input | Data input for buffer 3. TTL-compatible input accepting 0 to 5.5 V. Includes bus-hold on the input. |+| 10 | 3OE | input | Active-low output-enable for buffer 3. Drive low to enable the 3Y output; drive high to place 3Y in the high-impedance state. |+| 11 | 4Y | tri_state | 3-state buffered output for channel 4. Follows 4A when 4OE is low; high-impedance when 4OE is high. |+| 12 | 4A | input | Data input for buffer 4. TTL-compatible input accepting 0 to 5.5 V. Includes bus-hold on the input. |+| 13 | 4OE | input | Active-low output-enable for buffer 4. Drive low to enable the 4Y output; drive high to place 4Y in the high-impedance state. |+| 14 | VCC | power_in | Supply voltage input. Recommended operating range 2.7 V to 3.6 V (absolute max 4.6 V). Bypass locally with a 100 nF ceramic capacitor to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `SN74LVTH125PWRPW`+- `SN74LVTH125PWRPWR`+- `SN74LVTH125PWRD`+- `SN74LVTH125PWRDR`+- `SN74LVTH125PWRDBR`+- `SN74LVTH125PWRNSR`+- `SN74LVTH125PWRDGVR`+- `SN74LVTH125PWRRGYR`+- `SN74LVTH125PWRJ`+- `SN74LVTH125PWRW`+- `SN74LVTH125PWRFK`++## CAD (KiCad official)++- Symbol: `SN74LVTH125PWR`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvth125.pdf) (27 pp, sha256 `1b1840e18d1c1ea0`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvth125pwr-datasheet.pdf)

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