component
SN74LVC821APWR
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+60@@ -0,0 +1,60 @@+# SN74LVC821APWR++**Texas Instruments** · Flip Flops · TSSOP-24++SN74LVC821APWR from Texas Instruments, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Buffered active-low output enable: when OE is low the ten Q outputs are in a normal logic state, and when OE is high they are in the high-impedance state, and OE should be tied to VCC through a pullup resistor to ensure high-impedance during power up or power down. |+| 2 | 1D | input | Data input to flip-flop 1, which accepts input voltages up to 5.5 V and is captured on the positive transition of CLK. |+| 3 | 2D | input | Data input to flip-flop 2, which accepts input voltages up to 5.5 V and is captured on the positive transition of CLK. |+| 4 | 3D | input | Data input to flip-flop 3, which accepts input voltages up to 5.5 V and is captured on the positive transition of CLK. |+| 5 | 4D | input | Data input to flip-flop 4, which accepts input voltages up to 5.5 V and is captured on the positive transition of CLK. |+| 6 | 5D | input | Data input to flip-flop 5, which accepts input voltages up to 5.5 V and is captured on the positive transition of CLK. |+| 7 | 6D | input | Data input to flip-flop 6, which accepts input voltages up to 5.5 V and is captured on the positive transition of CLK. |+| 8 | 7D | input | Data input to flip-flop 7, which accepts input voltages up to 5.5 V and is captured on the positive transition of CLK. |+| 9 | 8D | input | Data input to flip-flop 8, which accepts input voltages up to 5.5 V and is captured on the positive transition of CLK. |+| 10 | 9D | input | Data input to flip-flop 9, which accepts input voltages up to 5.5 V and is captured on the positive transition of CLK. |+| 11 | 10D | input | Data input to flip-flop 10, which accepts input voltages up to 5.5 V and is captured on the positive transition of CLK. |+| 12 | GND | power_in | Ground reference; continuous current through VCC or GND is rated at ±100 mA. |+| 13 | CLK | input | Positive-edge clock: on the positive transition the device latches D data and presents true data on the Q outputs, with a minimum pulse duration of 3.3 ns and a maximum clock frequency of 150 MHz. |+| 14 | 10Q | tri_state | 3-state output of flip-flop 10, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA. |+| 15 | 9Q | tri_state | 3-state output of flip-flop 9, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA. |+| 16 | 8Q | tri_state | 3-state output of flip-flop 8, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA. |+| 17 | 7Q | tri_state | 3-state output of flip-flop 7, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA. |+| 18 | 6Q | tri_state | 3-state output of flip-flop 6, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA. |+| 19 | 5Q | tri_state | 3-state output of flip-flop 5, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA. |+| 20 | 4Q | tri_state | 3-state output of flip-flop 4, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA. |+| 21 | 3Q | tri_state | 3-state output of flip-flop 3, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA. |+| 22 | 2Q | tri_state | 3-state output of flip-flop 2, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA. |+| 23 | 1Q | tri_state | 3-state output of flip-flop 1, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA. |+| 24 | VCC | power_in | Supply voltage: operating range 1.65 V to 3.6 V, with data retention down to 1.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-24 |+| Category | Logic |+| Pins | 24 |++## CAD (KiCad official)++- Symbol: `SN74LVC821APWR`+- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`+- 3D model: TSSOP-24 (KiCad packages3D, STEP)+- 3D model files: `sn74lvc821apwr-etched.step` / `sn74lvc821apwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc821apwr.step` / `sn74lvc821apwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvc821a.pdf) (21 pp, sha256 `21c0d871fce0b9d0`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc821apwr-datasheet.pdf)
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continuous current through VCC or GND is rated at ±100 mA."+ },+ {+ "number": "13",+ "name": "CLK",+ "type": "input",+ "description": "Positive-edge clock: on the positive transition the device latches D data and presents true data on the Q outputs, with a minimum pulse duration of 3.3 ns and a maximum clock frequency of 150 MHz."+ },+ {+ "number": "14",+ "name": "10Q",+ "type": "tri_state",+ "description": "3-state output of flip-flop 10, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA."+ },+ {+ "number": "15",+ "name": "9Q",+ "type": "tri_state",+ "description": "3-state output of flip-flop 9, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA."+ },+ {+ "number": "16",+ "name": "8Q",+ "type": "tri_state",+ "description": "3-state output of flip-flop 8, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA."+ },+ {+ "number": "17",+ "name": "7Q",+ "type": "tri_state",+ "description": "3-state output of flip-flop 7, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA."+ },+ {+ "number": "18",+ "name": "6Q",+ "type": "tri_state",+ "description": "3-state output of flip-flop 6, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA."+ },+ {+ "number": "19",+ "name": "5Q",+ "type": "tri_state",+ "description": "3-state output of flip-flop 5, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA."+ },+ {+ "number": "20",+ "name": "4Q",+ "type": "tri_state",+ "description": "3-state output of flip-flop 4, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA."+ },+ {+ "number": "21",+ "name": "3Q",+ "type": "tri_state",+ "description": "3-state output of flip-flop 3, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA."+ },+ {+ "number": "22",+ "name": "2Q",+ "type": "tri_state",+ "description": "3-state output of flip-flop 2, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA."+ },+ {+ "number": "23",+ "name": "1Q",+ "type": "tri_state",+ "description": "3-state output of flip-flop 1, designed for driving highly capacitive or relatively low-impedance loads, with continuous output current rated at ±50 mA."+ },+ {+ "number": "24",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage: operating range 1.65 V to 3.6 V, with data retention down to 1.5 V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin numbers were mapped from the text-extracted TOP VIEW diagram (pins 1-12 listed down the left, 24; The datasheet gives no spec or pin-level data beyond the PW (TSSOP-24) package list for this MPN; no"+ ],+ "pages_sent": 21,+ "cost_usd": 0.0897,+ "at": "2026-10-08T17:05:36"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lvc821a.pdf",+ "pages": 21,+ "sha256": "21c0d871fce0b9d0",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 24,+ "described": 24,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74lvc821apwr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "706322f42d9793ebf28d5b80100a68bfa8769998a00b78acadf7af937fc1454f",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74lvc821apwr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 7.8,+ 0.97+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "18722edcf04dfa17e6864bede984403dad84d3f3c349868ad04ee6bc5fec2975",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}