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Initial commit: component/sn74lvc574apwr

Ray ·f2199e9eb4 ·
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README.mdadded+73
@@ -0,0 +1,73 @@+# SN74LVC574APWR++**Texas Instruments** · Flip Flops · TSSOP-20++SN74LVC574APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | Active-low output enable (OE). When low, the eight Q outputs are enabled; when high, all Q outputs are placed in the high-impedance (3-state) condition. Does not affect internal flip-flop operation. Tie to VCC through a pullup during power-up/down to guarantee Hi-Z. |+| 2 | 1D | input | Data input to flip-flop 1. Sampled on the rising edge of CLK and transferred to output 1Q. Inputs accept voltages up to 5.5 V. |+| 3 | 2D | input | Data input to flip-flop 2. Sampled on the rising edge of CLK and transferred to output 2Q. |+| 4 | 3D | input | Data input to flip-flop 3. Sampled on the rising edge of CLK and transferred to output 3Q. |+| 5 | 4D | input | Data input to flip-flop 4. Sampled on the rising edge of CLK and transferred to output 4Q. |+| 6 | 5D | input | Data input to flip-flop 5. Sampled on the rising edge of CLK and transferred to output 5Q. |+| 7 | 6D | input | Data input to flip-flop 6. Sampled on the rising edge of CLK and transferred to output 6Q. |+| 8 | 7D | input | Data input to flip-flop 7. Sampled on the rising edge of CLK and transferred to output 7Q. |+| 9 | 8D | input | Data input to flip-flop 8. Sampled on the rising edge of CLK and transferred to output 8Q. |+| 10 | GND | power_in | Ground reference (0 V). Common return for VCC and all input/output signals. |+| 11 | CLK | input | Clock input common to all eight flip-flops. Data on D inputs is transferred to Q outputs on the rising edge (positive transition) of CLK. Minimum pulse width 3.3 ns at VCC = 3.3 V; fmax up to 150 MHz. |+| 12 | 8Q | tri_state | 3-state output of flip-flop 8. Reflects last clocked value of 8D when OE is low; Hi-Z when OE is high. Drive capability of ±24 mA at VCC = 3 V. |+| 13 | 7Q | tri_state | 3-state output of flip-flop 7. Reflects last clocked value of 7D when OE is low; Hi-Z when OE is high. |+| 14 | 6Q | tri_state | 3-state output of flip-flop 6. Reflects last clocked value of 6D when OE is low; Hi-Z when OE is high. |+| 15 | 5Q | tri_state | 3-state output of flip-flop 5. Reflects last clocked value of 5D when OE is low; Hi-Z when OE is high. |+| 16 | 4Q | tri_state | 3-state output of flip-flop 4. Reflects last clocked value of 4D when OE is low; Hi-Z when OE is high. |+| 17 | 3Q | tri_state | 3-state output of flip-flop 3. Reflects last clocked value of 3D when OE is low; Hi-Z when OE is high. |+| 18 | 2Q | tri_state | 3-state output of flip-flop 2. Reflects last clocked value of 2D when OE is low; Hi-Z when OE is high. |+| 19 | 1Q | tri_state | 3-state output of flip-flop 1. Reflects last clocked value of 1D when OE is low; Hi-Z when OE is high. |+| 20 | VCC | power_in | Positive supply voltage, 1.65 V to 3.6 V operating range (SN74LVC574A). Decouple with a local bypass capacitor to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-20 |+| Category | Logic |+| Pins | 20 |++## Ordering variants++- `SN74LVC574APWRAPW`+- `SN74LVC574APWRAPWR`+- `SN74LVC574APWRAPWT`+- `SN74LVC574APWRADW`+- `SN74LVC574APWRADWR`+- `SN74LVC574APWRADBR`+- `SN74LVC574APWRADGVR`+- `SN74LVC574APWRANSR`+- `SN74LVC574APWRAN`+- `SN74LVC574APWRARGYR`+- `SN74LVC574APWRAGQNR`+- `SN74LVC574APWRAZQNR`+- `SN74LVC574APWRFK`+- `SN74LVC574APWRJ`+- `SN74LVC574APWRW`++## CAD (KiCad official)++- Symbol: `SN74LVC574APWR`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/sn74lvc574a.pdf) (35 pp, sha256 `e6aad666cf80743a`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc574apwr-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "sn74lvc574apwr",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "sn74lvc574apwr"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "sn74lvc574apwr.kicad_sym",+    "sn74lvc574apwr.kicad_mod",+    "sn74lvc574apwr.glb",+    "sn74lvc574apwr.step",+    "sn74lvc574apwr.lbr",+    "docs/hero.png",+    "docs/sn74lvc574apwr-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file