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SN74LVC32AQPWRG4Q1
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Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+51@@ -0,0 +1,51 @@+# SN74LVC32AQPWRG4Q1++**Texas Instruments** · Logic Gates · TSSOP-14++SN74LVC32AQPWRG4Q1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Channel 1 data input A of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating. |+| 2 | 1B | input | Channel 1 data input B of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating. |+| 3 | 1Y | output | Channel 1 output Y; rated for IOH of -12 mA at VCC = 2.7 V and -24 mA at VCC = 3 V, and IOL of 12 mA at 2.7 V and 24 mA at 3 V. |+| 4 | 2A | input | Channel 2 data input A of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating. |+| 5 | 2B | input | Channel 2 data input B of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating. |+| 6 | 2Y | output | Channel 2 output Y; rated for IOH of -12 mA at VCC = 2.7 V and -24 mA at VCC = 3 V, and IOL of 12 mA at 2.7 V and 24 mA at 3 V. |+| 7 | GND | power_in | Ground reference for the device. |+| 8 | 3Y | output | Channel 3 output Y; rated for IOH of -12 mA at VCC = 2.7 V and -24 mA at VCC = 3 V, and IOL of 12 mA at 2.7 V and 24 mA at 3 V. |+| 9 | 3A | input | Channel 3 data input A of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating. |+| 10 | 3B | input | Channel 3 data input B of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating. |+| 11 | 4Y | output | Channel 4 output Y; rated for IOH of -12 mA at VCC = 2.7 V and -24 mA at VCC = 3 V, and IOL of 12 mA at 2.7 V and 24 mA at 3 V. |+| 12 | 4A | input | Channel 4 data input A of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating. |+| 13 | 4B | input | Channel 4 data input B of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating. |+| 14 | VCC | power_in | Positive supply; operating range 2 V to 3.6 V, with a 0.1 µF bypass capacitor recommended close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-14 |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `SN74LVC32AQPWRG4Q1`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `sn74lvc32aqpwrg4q1-etched.step` / `sn74lvc32aqpwrg4q1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `sn74lvc32aqpwrg4q1.step` / `sn74lvc32aqpwrg4q1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/sn74lvc32a-q1) (25 pp, sha256 `3eaa7b050b5bf4a6`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/sn74lvc32aqpwrg4q1-datasheet.pdf)
page.jsonadded+236@@ -0,0 +1,236 @@+{+ "slug": "sn74lvc32aqpwrg4q1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "sn74lvc32aqpwrg4q1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "sn74lvc32aqpwrg4q1.kicad_sym",+ "sn74lvc32aqpwrg4q1.kicad_mod",+ "sn74lvc32aqpwrg4q1.glb",+ "sn74lvc32aqpwrg4q1.step",+ "sn74lvc32aqpwrg4q1.lbr",+ "docs/hero.png",+ "docs/sn74lvc32aqpwrg4q1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "sn74lvc32aqpwrg4q1-hero.glb",+ "sn74lvc32aqpwrg4q1-hero.overlay.json"+ ],+ "component": {+ "mpn": "SN74LVC32AQPWRG4Q1",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-14",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/cn/lit/gpn/sn74lvc32a-q1",+ "parts": {+ "symbol": "sn74lvc32aqpwrg4q1.kicad_sym",+ "footprint": "sn74lvc32aqpwrg4q1.kicad_mod",+ "model_3d": "sn74lvc32aqpwrg4q1-hero.glb",+ "model_3d_plain": "sn74lvc32aqpwrg4q1.glb",+ "model_3d_step": "sn74lvc32aqpwrg4q1-etched.step",+ "model_3d_step_plain": "sn74lvc32aqpwrg4q1.step",+ "lbr": "sn74lvc32aqpwrg4q1.lbr"+ },+ "distributor_links": {+ "lcsc": "C2867928",+ "digikey": "296-SN74LVC32AQPWRG4Q1TR-ND",+ "mouser": "595-74LVC32AQPWRG4Q1"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T16:48:48Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-SN74LVC32AQPWRG4Q1TR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-74LVC32AQPWRG4Q1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "1A",+ "type": "input",+ "description": "Channel 1 data input A of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating."+ },+ {+ "number": "2",+ "name": "1B",+ "type": "input",+ "description": "Channel 1 data input B of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating."+ },+ {+ "number": "3",+ "name": "1Y",+ "type": "output",+ "description": "Channel 1 output Y; rated for IOH of -12 mA at VCC = 2.7 V and -24 mA at VCC = 3 V, and IOL of 12 mA at 2.7 V and 24 mA at 3 V."+ },+ {+ "number": "4",+ "name": "2A",+ "type": "input",+ "description": "Channel 2 data input A of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating."+ },+ {+ "number": "5",+ "name": "2B",+ "type": "input",+ "description": "Channel 2 data input B of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating."+ },+ {+ "number": "6",+ "name": "2Y",+ "type": "output",+ "description": "Channel 2 output Y; rated for IOH of -12 mA at VCC = 2.7 V and -24 mA at VCC = 3 V, and IOL of 12 mA at 2.7 V and 24 mA at 3 V."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device."+ },+ {+ "number": "8",+ "name": "3Y",+ "type": "output",+ "description": "Channel 3 output Y; rated for IOH of -12 mA at VCC = 2.7 V and -24 mA at VCC = 3 V, and IOL of 12 mA at 2.7 V and 24 mA at 3 V."+ },+ {+ "number": "9",+ "name": "3A",+ "type": "input",+ "description": "Channel 3 data input A of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating."+ },+ {+ "number": "10",+ "name": "3B",+ "type": "input",+ "description": "Channel 3 data input B of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating."+ },+ {+ "number": "11",+ "name": "4Y",+ "type": "output",+ "description": "Channel 4 output Y; rated for IOH of -12 mA at VCC = 2.7 V and -24 mA at VCC = 3 V, and IOL of 12 mA at 2.7 V and 24 mA at 3 V."+ },+ {+ "number": "12",+ "name": "4A",+ "type": "input",+ "description": "Channel 4 data input A of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating."+ },+ {+ "number": "13",+ "name": "4B",+ "type": "input",+ "description": "Channel 4 data input B of the OR gate; inputs accept 0 V to 5.5 V and must not be left floating."+ },+ {+ "number": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply; operating range 2 V to 3.6 V, with a 0.1 µF bypass capacitor recommended close to the pin."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin-to-function mapping for the TSSOP-14 (PW) package is taken from Table 3-1 (Pin Functions) on pag; The datasheet is a Chinese translation of the English SCAS706 document; the English original was not; The thermal pad note on page 3 applies only to the BQA (WQFN) package. The PW package has no exposed"+ ],+ "pages_sent": 25,+ "cost_usd": 0.0856,+ "at": "2026-10-08T16:48:30"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/sn74lvc32a-q1",+ "pages": 25,+ "sha256": "3eaa7b050b5bf4a6",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "sn74lvc32aqpwrg4q1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3ee5786aae56190997aa793ba3cfc003fd616782770e29719b4562f012982245",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "sn74lvc32aqpwrg4q1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "77ef5c7e0df1222a2d2ae5ae90d724df61109080a6192001b7faeb6e160f431a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}