component
SN74LVC2G74DCUR
Public Made by Adomby adom
Texas Instruments Flip Flops, VSSOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+116−8@@ -1,13 +1,126 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74lvc2g74dcur",+ "title": "SN74LVC2G74DCUR",+ "brief": "Texas Instruments Flip Flops, VSSOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Texas Instruments Flip Flops, VSSOP-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "sn74lvc2g74dcur" ],+ "component": {+ "mpn": "SN74LVC2G74DCUR",+ "manufacturer": "Texas Instruments",+ "package": "VSSOP-8",+ "pin_count": 8,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://www.ti.com/lit/ds/symlink/sn74lvc2g74dcur.pdf",+ "parts": {+ "symbol": "sn74lvc2g74dcur.kicad_sym",+ "footprint": "sn74lvc2g74dcur.kicad_mod",+ "model_3d": "sn74lvc2g74dcur.glb",+ "model_3d_step": "sn74lvc2g74dcur.step",+ "lbr": "sn74lvc2g74dcur.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "CLK",+ "type": "input",+ "description": "Clock input. Data at D is transferred to Q on the positive-going edge of CLK when PRE and CLR are inactive (high). Accepts input voltages up to 5.5 V regardless of VCC."+ },+ {+ "number": "2",+ "name": "D",+ "type": "input",+ "description": "Data input. Sampled on the rising edge of CLK and transferred to Q when PRE and CLR are inactive high. Input tolerant to 5.5 V."+ },+ {+ "number": "3",+ "name": "~{Q}",+ "type": "output",+ "description": "Complementary (inverted) flip-flop output. Drives \u00b124 mA at VCC = 3.3 V. Goes high when the internal Q latch is reset by CLR = L."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V) for the device."+ },+ {+ "number": "5",+ "name": "Q",+ "type": "output",+ "description": "True flip-flop output. Reflects the state of the D input following the rising edge of CLK. Drives \u00b124 mA at VCC = 3.3 V."+ },+ {+ "number": "6",+ "name": "~{CLR}",+ "type": "input",+ "description": "Active-low asynchronous clear input. A low level forces Q low regardless of CLK or D. Must be held high for normal clocked operation."+ },+ {+ "number": "7",+ "name": "~{PRE}",+ "type": "input",+ "description": "Active-low asynchronous preset input. A low level forces Q high regardless of CLK or D. Must be held high for normal clocked operation."+ },+ {+ "number": "8",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. Operating range 1.65 V to 5.5 V; data retention down to 1.5 V. Bypass locally with a 0.1 \u00b5F ceramic capacitor to GND."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/sn74lvc2g74dcur.pdf",+ "pages": 18,+ "sha256": "5bb76431d38ce5ae",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Texas Instruments",+ "Package": "VSSOP-8",+ "Category": "Logic",+ "Pins": "8"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74lvc2g74dcur"+ ],+ "discovery_pitch": "SN74LVC2G74DCUR (Texas Instruments) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +138,5 @@ "docs/sn74lvc2g74dcur-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }