← Commit history

Publish 0.2.0

Ray ·8ad412cbf6 ·2mo ago ·parent bdcda9f
3 files changed +25−11
README.md+14
@@ -37,6 +37,20 @@ SN74LVC2G04DCKR from Texas Instruments, in a SOT-363-6. Pinout and pin descripti - Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6` - 3D model: SOT-363-6 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`sn74lvc2g04dckr.step`](sn74lvc2g04dckr.step) | 99 KB | You want the bare part, or you mark your own boards. |+| [`sn74lvc2g04dckr-etched.step`](sn74lvc2g04dckr-etched.step) | 2.5 MB | You want the part with `SN74LVC2G04DCKR` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 634 faces against 117 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance  Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1
@@ -1,6 +1,6 @@ {   "slug": "sn74lvc2g04dckr",-  "version": "0.1.0",+  "version": "0.2.0",   "type": "component",   "description": "UMW Inverters, SC70-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "tags": [
page.json+10−10
@@ -4,7 +4,7 @@   "slug": "sn74lvc2g04dckr",   "title": "SN74LVC2G04DCKR",   "brief": "Texas Instruments Inverters, SOT-363-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.2.0",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -35,7 +35,7 @@         "number": "1",         "name": "INA1",         "type": "input",-        "description": "Logic input to inverter gate 1. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH \u2265 0.7\u00b7VCC (VCC \u2265 2.3V), VIL \u2264 0.3\u00b7VCC. Input leakage \u00b11 \u00b5A max."+        "description": "Logic input to inverter gate 1. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH ≥ 0.7·VCC (VCC ≥ 2.3V), VIL ≤ 0.3·VCC. Input leakage ±1 µA max."       },       {         "number": "2",@@ -47,25 +47,25 @@         "number": "3",         "name": "INA2",         "type": "input",-        "description": "Logic input to inverter gate 2. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH \u2265 0.7\u00b7VCC (VCC \u2265 2.3V), VIL \u2264 0.3\u00b7VCC."+        "description": "Logic input to inverter gate 2. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH ≥ 0.7·VCC (VCC ≥ 2.3V), VIL ≤ 0.3·VCC."       },       {         "number": "4",         "name": "Y2",         "type": "output",-        "description": "Inverted logic output of gate 2 (Y2 = /INA2). Push-pull CMOS output with \u00b124 mA balanced sink/source capability. VOH \u2265 VCC\u22120.1V at 100 \u00b5A; VOL \u2264 0.55V at 24 mA (VCC = 3V)."+        "description": "Inverted logic output of gate 2 (Y2 = /INA2). Push-pull CMOS output with ±24 mA balanced sink/source capability. VOH ≥ VCC−0.1V at 100 µA; VOL ≤ 0.55V at 24 mA (VCC = 3V)."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply. Operating range 1.65V to 5.5V; absolute maximum 7V. Quiescent supply current ICC \u2264 10 \u00b5A. Bypass with a 0.1 \u00b5F ceramic capacitor to GND close to the pin."+        "description": "Positive supply. Operating range 1.65V to 5.5V; absolute maximum 7V. Quiescent supply current ICC ≤ 10 µA. Bypass with a 0.1 µF ceramic capacitor to GND close to the pin."       },       {         "number": "6",         "name": "Y1",         "type": "output",-        "description": "Inverted logic output of gate 1 (Y1 = /INA1). Push-pull CMOS output with \u00b124 mA balanced sink/source capability. VOH \u2265 VCC\u22120.1V at 100 \u00b5A; VOL \u2264 0.55V at 24 mA (VCC = 3V)."+        "description": "Inverted logic output of gate 1 (Y1 = /INA1). Push-pull CMOS output with ±24 mA balanced sink/source capability. VOH ≥ VCC−0.1V at 100 µA; VOL ≤ 0.55V at 24 mA (VCC = 3V)."       }     ],     "provenance": {@@ -139,9 +139,9 @@     "docs/hero.png",     "docs/sn74lvc2g04dckr-datasheet.pdf",     "viewers/symbol.html",-    "viewers/footprint.html"+    "viewers/footprint.html",+    "pads.json"   ],-  "visibility": {-    "public": true-  }+  "visibility": "public",+  "description": "UMW Inverters, SC70-6. Datasheet-verified pinout, KiCad symbol/footprint/3D." }\ No newline at end of file