component
SN74LVC2G04DCKR
Public Made by Adomby adom
Texas Instruments Inverters, SOT-363-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+104−8@@ -1,13 +1,114 @@ {+ "schema_version": 1,+ "type": "component", "slug": "sn74lvc2g04dckr",+ "title": "SN74LVC2G04DCKR",+ "brief": "UMW Inverters, SC70-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "UMW Inverters, SC70-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "sn74lvc2g04dckr" ],+ "component": {+ "mpn": "SN74LVC2G04DCKR",+ "manufacturer": "UMW",+ "package": "SC70-6",+ "pin_count": 6,+ "category": "Logic",+ "subcategory": "Inverters",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2311091745_UMW-Youtai-Semiconductor-Co---Ltd--SN74LVC2G04DCKR-UMW_C7394041.pdf",+ "parts": {+ "symbol": "sn74lvc2g04dckr.kicad_sym",+ "footprint": "sn74lvc2g04dckr.kicad_mod",+ "model_3d": "sn74lvc2g04dckr.glb",+ "model_3d_step": "sn74lvc2g04dckr.step",+ "lbr": "sn74lvc2g04dckr.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "INA1",+ "type": "input",+ "description": "Logic input to inverter gate 1. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH \u2265 0.7\u00b7VCC (VCC \u2265 2.3V), VIL \u2264 0.3\u00b7VCC. Input leakage \u00b11 \u00b5A max."+ },+ {+ "number": "2",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). Common return for VCC and all logic signals."+ },+ {+ "number": "3",+ "name": "INA2",+ "type": "input",+ "description": "Logic input to inverter gate 2. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH \u2265 0.7\u00b7VCC (VCC \u2265 2.3V), VIL \u2264 0.3\u00b7VCC."+ },+ {+ "number": "4",+ "name": "Y2",+ "type": "output",+ "description": "Inverted logic output of gate 2 (Y2 = /INA2). Push-pull CMOS output with \u00b124 mA balanced sink/source capability. VOH \u2265 VCC\u22120.1V at 100 \u00b5A; VOL \u2264 0.55V at 24 mA (VCC = 3V)."+ },+ {+ "number": "5",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply. Operating range 1.65V to 5.5V; absolute maximum 7V. Quiescent supply current ICC \u2264 10 \u00b5A. Bypass with a 0.1 \u00b5F ceramic capacitor to GND close to the pin."+ },+ {+ "number": "6",+ "name": "Y1",+ "type": "output",+ "description": "Inverted logic output of gate 1 (Y1 = /INA1). Push-pull CMOS output with \u00b124 mA balanced sink/source capability. VOH \u2265 VCC\u22120.1V at 100 \u00b5A; VOL \u2264 0.55V at 24 mA (VCC = 3V)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2311091745_UMW-Youtai-Semiconductor-Co---Ltd--SN74LVC2G04DCKR-UMW_C7394041.pdf",+ "pages": 11,+ "sha256": "31717c0fad81eae7",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 6,+ "described": 6,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "UMW",+ "Package": "SC70-6",+ "Category": "Logic",+ "Pins": "6"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "sn74lvc2g04dckr"+ ],+ "discovery_pitch": "SN74LVC2G04DCKR (UMW) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +126,5 @@ "docs/sn74lvc2g04dckr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }