component
SN74LVC2G04DCKR
Public Made by Adomby adom
Texas Instruments Inverters, SOT-363-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (DIGIKEY_PN 296-13262-2-ND, LCSC_PN C105251). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.
2 files changed
+30−8
page.json+9−6@@ -26,13 +26,16 @@ "model_3d_step": "sn74lvc2g04dckr.step", "lbr": "sn74lvc2g04dckr.lbr" },- "distributor_links": {},+ "distributor_links": {+ "digikey": "296-13262-2-ND",+ "lcsc": "C105251"+ }, "pins": [ { "number": "1", "name": "INA1", "type": "input",- "description": "Logic input to inverter gate 1. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH ≥ 0.7·VCC (VCC ≥ 2.3V), VIL ≤ 0.3·VCC. Input leakage ±1 µA max."+ "description": "Logic input to inverter gate 1. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH \u2265 0.7\u00b7VCC (VCC \u2265 2.3V), VIL \u2264 0.3\u00b7VCC. Input leakage \u00b11 \u00b5A max." }, { "number": "2",@@ -44,25 +47,25 @@ "number": "3", "name": "INA2", "type": "input",- "description": "Logic input to inverter gate 2. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH ≥ 0.7·VCC (VCC ≥ 2.3V), VIL ≤ 0.3·VCC."+ "description": "Logic input to inverter gate 2. CMOS input, overvoltage tolerant up to 5.5V independent of VCC. VIH \u2265 0.7\u00b7VCC (VCC \u2265 2.3V), VIL \u2264 0.3\u00b7VCC." }, { "number": "4", "name": "Y2", "type": "output",- "description": "Inverted logic output of gate 2 (Y2 = /INA2). Push-pull CMOS output with ±24 mA balanced sink/source capability. VOH ≥ VCC−0.1V at 100 µA; VOL ≤ 0.55V at 24 mA (VCC = 3V)."+ "description": "Inverted logic output of gate 2 (Y2 = /INA2). Push-pull CMOS output with \u00b124 mA balanced sink/source capability. VOH \u2265 VCC\u22120.1V at 100 \u00b5A; VOL \u2264 0.55V at 24 mA (VCC = 3V)." }, { "number": "5", "name": "VCC", "type": "power_in",- "description": "Positive supply. Operating range 1.65V to 5.5V; absolute maximum 7V. Quiescent supply current ICC ≤ 10 µA. Bypass with a 0.1 µF ceramic capacitor to GND close to the pin."+ "description": "Positive supply. Operating range 1.65V to 5.5V; absolute maximum 7V. Quiescent supply current ICC \u2264 10 \u00b5A. Bypass with a 0.1 \u00b5F ceramic capacitor to GND close to the pin." }, { "number": "6", "name": "Y1", "type": "output",- "description": "Inverted logic output of gate 1 (Y1 = /INA1). Push-pull CMOS output with ±24 mA balanced sink/source capability. VOH ≥ VCC−0.1V at 100 µA; VOL ≤ 0.55V at 24 mA (VCC = 3V)."+ "description": "Inverted logic output of gate 1 (Y1 = /INA1). Push-pull CMOS output with \u00b124 mA balanced sink/source capability. VOH \u2265 VCC\u22120.1V at 100 \u00b5A; VOL \u2264 0.55V at 24 mA (VCC = 3V)." } ], "provenance": {
sn74lvc2g04dckr.lbr+21−2@@ -60,6 +60,18 @@ <smd name="4" x="0.8375" y="-0.6500" dx="1.0250" dy="0.3500" layer="1"/> <smd name="5" x="0.8375" y="-0.0000" dx="1.0250" dy="0.3500" layer="1"/> <smd name="6" x="0.8375" y="0.6500" dx="1.0250" dy="0.3500" layer="1"/>+ <polygon width="0.1200" layer="21">+ <vertex x="-1.1800" y="1.0900"/>+ <vertex x="-1.3200" y="1.2800"/>+ <vertex x="-1.0400" y="1.2800"/>+ </polygon>+ <polygon width="0.1000" layer="51">+ <vertex x="-0.3125" y="1.0000"/>+ <vertex x="0.6250" y="1.0000"/>+ <vertex x="0.6250" y="-1.0000"/>+ <vertex x="-0.6250" y="-1.0000"/>+ <vertex x="-0.6250" y="0.6875"/>+ </polygon> <wire x1="-0.7350" y1="1.1100" x2="0.7350" y2="1.1100" width="0.1200" layer="21"/> <wire x1="-0.7350" y1="1.0850" x2="-0.7350" y2="1.1100" width="0.1200" layer="21"/> <wire x1="-0.7350" y1="-1.1100" x2="-0.7350" y2="-1.0850" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@ <wire x1="0.7350" y1="-1.1100" x2="-0.7350" y2="-1.1100" width="0.1200" layer="21"/> <text x="0" y="1.763" size="1.27" layer="25" align="bottom-center">>NAME</text> <text x="0" y="-1.763" size="1.27" layer="27" align="top-center">>VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.1800" y="1.0900"/><vertex x="-1.3200" y="1.2800"/><vertex x="-1.0400" y="1.2800"/></polygon></package>+</package> </packages> <symbols> <symbol name="SN74LVC2G04DCKR">@@ -102,7 +114,14 @@ <connect gate="G$1" pin="VCC" pad="5"/> <connect gate="G$1" pin="Y2" pad="4"/> </connects>- <technologies><technology name=""/></technologies>+ <technologies>+ <technology name="">+ <attribute name="MPN" value="SN74LVC2G04DCKR" constant="no"/>+ <attribute name="MANUFACTURER" value="Texas Instruments" constant="no"/>+ <attribute name="DIGIKEY_PN" value="296-13262-2-ND" constant="no"/>+ <attribute name="LCSC_PN" value="C105251" constant="no"/>+ </technology>+ </technologies> </device> </devices> </deviceset>