← Commit history

orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (DIGIKEY_PN 4518-SN74LVC1G86DCKRTR-ND). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.

Ray ·815ac0ba2d ·2mo ago ·parent 6d4a0c0
2 files changed +27−7
page.json+7−5
@@ -26,19 +26,21 @@       "model_3d_step": "sn74lvc1g86dckr.step",       "lbr": "sn74lvc1g86dckr.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "digikey": "4518-SN74LVC1G86DCKRTR-ND"+    },     "pins": [       {         "number": "1",         "name": "INB",         "type": "input",-        "description": "B-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7·VCC (VCC 2.3-5.5 V); input leakage ±1 µA max."+        "description": "B-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7\u00b7VCC (VCC 2.3-5.5 V); input leakage \u00b11 \u00b5A max."       },       {         "number": "2",         "name": "INA",         "type": "input",-        "description": "A-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7·VCC (VCC 2.3-5.5 V); input leakage ±1 µA max."+        "description": "A-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7\u00b7VCC (VCC 2.3-5.5 V); input leakage \u00b11 \u00b5A max."       },       {         "number": "3",@@ -50,13 +52,13 @@         "number": "4",         "name": "Y",         "type": "output",-        "description": "XOR output (Y = A ⊕ B). Push-pull CMOS output, sinks up to 24 mA (IOL) and sources up to 24 mA (IOH) at VCC=3 V; pullup on this pin may be tied to a rail between 0 and 7 V."+        "description": "XOR output (Y = A \u2295 B). Push-pull CMOS output, sinks up to 24 mA (IOL) and sources up to 24 mA (IOH) at VCC=3 V; pullup on this pin may be tied to a rail between 0 and 7 V."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply input. Recommended operating range 1.65 V to 5.5 V (absolute max 7 V). Bypass with a 0.1 µF ceramic capacitor to GND close to the pin."+        "description": "Positive supply input. Recommended operating range 1.65 V to 5.5 V (absolute max 7 V). Bypass with a 0.1 \u00b5F ceramic capacitor to GND close to the pin."       }     ],     "provenance": {
sn74lvc1g86dckr.lbr+20−2
@@ -59,6 +59,18 @@   <smd name="3" x="-0.8375" y="-0.6500" dx="1.0250" dy="0.3500" layer="1"/>   <smd name="4" x="0.8375" y="-0.6500" dx="1.0250" dy="0.3500" layer="1"/>   <smd name="5" x="0.8375" y="0.6500" dx="1.0250" dy="0.3500" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-1.1800" y="1.0900"/>+    <vertex x="-1.3200" y="1.2800"/>+    <vertex x="-1.0400" y="1.2800"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.3125" y="1.0000"/>+    <vertex x="0.6250" y="1.0000"/>+    <vertex x="0.6250" y="-1.0000"/>+    <vertex x="-0.6250" y="-1.0000"/>+    <vertex x="-0.6250" y="0.6875"/>+  </polygon>   <wire x1="-0.7350" y1="1.1100" x2="0.7350" y2="1.1100" width="0.1200" layer="21"/>   <wire x1="-0.7350" y1="1.0850" x2="-0.7350" y2="1.1100" width="0.1200" layer="21"/>   <wire x1="-0.7350" y1="-1.1100" x2="-0.7350" y2="-1.0850" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@   <wire x1="0.7350" y1="-1.1100" x2="-0.7350" y2="-1.1100" width="0.1200" layer="21"/>   <text x="0" y="1.763" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-1.763" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.1800" y="1.0900"/><vertex x="-1.3200" y="1.2800"/><vertex x="-1.0400" y="1.2800"/></polygon></package>+</package> </packages> <symbols> <symbol name="SN74LVC1G86DCKR">@@ -100,7 +112,13 @@         <connect gate="G$1" pin="VCC" pad="5"/>         <connect gate="G$1" pin="Y" pad="4"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="SN74LVC1G86DCKR" constant="no"/>+          <attribute name="MANUFACTURER" value="UMW" constant="no"/>+          <attribute name="DIGIKEY_PN" value="4518-SN74LVC1G86DCKRTR-ND" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>