component
SN74LVC1G86DCKR
Public Made by Adomby adom
UMW Gates, SC-70-5. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.md+14@@ -35,6 +35,20 @@ SN74LVC1G86DCKR from UMW, in a SC-70-5. Pinout and pin descriptions extracted fr - Footprint: `Package_TO_SOT_SMD:SOT-353_SC-70-5` - 3D model: SC-70-5 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`sn74lvc1g86dckr.step`](sn74lvc1g86dckr.step) | 87 KB | You want the bare part, or you mark your own boards. |+| [`sn74lvc1g86dckr-etched.step`](sn74lvc1g86dckr-etched.step) | 2.6 MB | You want the part with `SN74LVC1G86DCKR` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 637 faces against 102 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1@@ -1,6 +1,6 @@ { "slug": "sn74lvc1g86dckr",- "version": "0.1.0",+ "version": "0.2.0", "type": "component", "description": "Unknown Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "tags": [
page.json+10−7@@ -4,7 +4,7 @@ "slug": "sn74lvc1g86dckr", "title": "SN74LVC1G86DCKR", "brief": "UMW Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.2.0", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -34,13 +34,13 @@ "number": "1", "name": "INB", "type": "input",- "description": "B-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7\u00b7VCC (VCC 2.3-5.5 V); input leakage \u00b11 \u00b5A max."+ "description": "B-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7·VCC (VCC 2.3-5.5 V); input leakage ±1 µA max." }, { "number": "2", "name": "INA", "type": "input",- "description": "A-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7\u00b7VCC (VCC 2.3-5.5 V); input leakage \u00b11 \u00b5A max."+ "description": "A-input of the 2-input XOR gate. LVCMOS/TTL compatible logic input, tolerant to VIN up to 7 V independent of VCC. VIH = 0.7·VCC (VCC 2.3-5.5 V); input leakage ±1 µA max." }, { "number": "3",@@ -52,13 +52,13 @@ "number": "4", "name": "Y", "type": "output",- "description": "XOR output (Y = A \u2295 B). Push-pull CMOS output, sinks up to 24 mA (IOL) and sources up to 24 mA (IOH) at VCC=3 V; pullup on this pin may be tied to a rail between 0 and 7 V."+ "description": "XOR output (Y = A ⊕ B). Push-pull CMOS output, sinks up to 24 mA (IOL) and sources up to 24 mA (IOH) at VCC=3 V; pullup on this pin may be tied to a rail between 0 and 7 V." }, { "number": "5", "name": "VCC", "type": "power_in",- "description": "Positive supply input. Recommended operating range 1.65 V to 5.5 V (absolute max 7 V). Bypass with a 0.1 \u00b5F ceramic capacitor to GND close to the pin."+ "description": "Positive supply input. Recommended operating range 1.65 V to 5.5 V (absolute max 7 V). Bypass with a 0.1 µF ceramic capacitor to GND close to the pin." } ], "provenance": {@@ -132,6 +132,9 @@ "docs/hero.png", "docs/sn74lvc1g86dckr-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"- ]+ "viewers/footprint.html",+ "pads.json"+ ],+ "description": "Unknown Gates, SC-70-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "visibility": "public" }