component
SN74LVC1G332DBVR
Public Made by Adomby adom
Texas Instruments Gates, SOT-23-6. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+10−7@@ -32,37 +32,37 @@ "number": "1", "name": "A", "type": "input",- "description": "Logic input A of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. VIH = 0.7\u00d7VCC and VIL = 0.3\u00d7VCC at VCC = 4.5-5.5 V. Input leakage \u00b15 \u00b5A max."+ "description": "Logic input A of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. VIH = 0.7×VCC and VIL = 0.3×VCC at VCC = 4.5-5.5 V. Input leakage ±5 µA max." }, { "number": "2", "name": "GND", "type": "power_in",- "description": "Ground reference for the device. Continuous current through GND rated \u00b1100 mA max."+ "description": "Ground reference for the device. Continuous current through GND rated ±100 mA max." }, { "number": "3", "name": "B", "type": "input",- "description": "Logic input B of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. Input leakage \u00b15 \u00b5A max, Ci \u2248 3.5 pF at 3.3 V."+ "description": "Logic input B of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. Input leakage ±5 µA max, Ci ≈ 3.5 pF at 3.3 V." }, { "number": "4", "name": "Y", "type": "output",- "description": "OR-gate output, Y = A + B + C. Push-pull CMOS output rated \u00b124 mA at VCC = 3 V (\u00b132 mA at VCC = 4.5 V). VOH \u2248 VCC \u2212 0.1 V at IOH = \u2212100 \u00b5A."+ "description": "OR-gate output, Y = A + B + C. Push-pull CMOS output rated ±24 mA at VCC = 3 V (±32 mA at VCC = 4.5 V). VOH ≈ VCC − 0.1 V at IOH = −100 µA." }, { "number": "5", "name": "VCC", "type": "power_in",- "description": "Supply voltage input. Operating range 1.65 V to 5.5 V; data-retention minimum 1.5 V. Quiescent supply current ICC \u2264 10 \u00b5A. Bypass with a local 0.1 \u00b5F ceramic capacitor to GND."+ "description": "Supply voltage input. Operating range 1.65 V to 5.5 V; data-retention minimum 1.5 V. Quiescent supply current ICC ≤ 10 µA. Bypass with a local 0.1 µF ceramic capacitor to GND." }, { "number": "6", "name": "C", "type": "input",- "description": "Logic input C of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC (supports down-translation to VCC). Input leakage \u00b15 \u00b5A max."+ "description": "Logic input C of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC (supports down-translation to VCC). Input leakage ±5 µA max." } ], "provenance": {@@ -126,5 +126,8 @@ "docs/sn74lvc1g332dbvr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }