SN74LVC1G332DBVR

@@ -26,43 +26,46 @@       "model_3d_step": "sn74lvc1g332dbvr.step",       "lbr": "sn74lvc1g332dbvr.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "digikey": "296-18587-2-ND",+      "lcsc": "C43368"+    },     "pins": [       {         "number": "1",         "name": "A",         "type": "input",-        "description": "Logic input A of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. VIH = 0.7×VCC and VIL = 0.3×VCC at VCC = 4.5-5.5 V. Input leakage ±5 µA max."+        "description": "Logic input A of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. VIH = 0.7\u00d7VCC and VIL = 0.3\u00d7VCC at VCC = 4.5-5.5 V. Input leakage \u00b15 \u00b5A max."       },       {         "number": "2",         "name": "GND",         "type": "power_in",-        "description": "Ground reference for the device. Continuous current through GND rated ±100 mA max."+        "description": "Ground reference for the device. Continuous current through GND rated \u00b1100 mA max."       },       {         "number": "3",         "name": "B",         "type": "input",-        "description": "Logic input B of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. Input leakage ±5 µA max, Ci ≈ 3.5 pF at 3.3 V."+        "description": "Logic input B of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. Input leakage \u00b15 \u00b5A max, Ci \u2248 3.5 pF at 3.3 V."       },       {         "number": "4",         "name": "Y",         "type": "output",-        "description": "OR-gate output, Y = A + B + C. Push-pull CMOS output rated ±24 mA at VCC = 3 V (±32 mA at VCC = 4.5 V). VOH ≈ VCC − 0.1 V at IOH = −100 µA."+        "description": "OR-gate output, Y = A + B + C. Push-pull CMOS output rated \u00b124 mA at VCC = 3 V (\u00b132 mA at VCC = 4.5 V). VOH \u2248 VCC \u2212 0.1 V at IOH = \u2212100 \u00b5A."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Supply voltage input. Operating range 1.65 V to 5.5 V; data-retention minimum 1.5 V. Quiescent supply current ICC ≤ 10 µA. Bypass with a local 0.1 µF ceramic capacitor to GND."+        "description": "Supply voltage input. Operating range 1.65 V to 5.5 V; data-retention minimum 1.5 V. Quiescent supply current ICC \u2264 10 \u00b5A. Bypass with a local 0.1 \u00b5F ceramic capacitor to GND."       },       {         "number": "6",         "name": "C",         "type": "input",-        "description": "Logic input C of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC (supports down-translation to VCC). Input leakage ±5 µA max."+        "description": "Logic input C of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC (supports down-translation to VCC). Input leakage \u00b15 \u00b5A max."       }     ],     "provenance": {

@@ -60,6 +60,18 @@   <smd name="4" x="1.1375" y="-0.9500" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="5" x="1.1375" y="-0.0000" dx="1.3250" dy="0.6000" layer="1"/>   <smd name="6" x="1.1375" y="0.9500" dx="1.3250" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-1.4500" y="1.5100"/>+    <vertex x="-1.6900" y="1.8400"/>+    <vertex x="-1.2100" y="1.8400"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.4000" y="1.4500"/>+    <vertex x="0.8000" y="1.4500"/>+    <vertex x="0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="-1.4500"/>+    <vertex x="-0.8000" y="1.0500"/>+  </polygon>   <wire x1="-0.9100" y1="1.5600" x2="0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="1.5100" x2="-0.9100" y2="1.5600" width="0.1200" layer="21"/>   <wire x1="-0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5100" width="0.1200" layer="21"/>@@ -68,7 +80,7 @@   <wire x1="0.9100" y1="-1.5600" x2="-0.9100" y2="-1.5600" width="0.1200" layer="21"/>   <text x="0" y="2.212" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-2.212" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-1.4500" y="1.5100"/><vertex x="-1.6900" y="1.8400"/><vertex x="-1.2100" y="1.8400"/></polygon></package>+</package> </packages> <symbols> <symbol name="SN74LVC1G332DBVR">@@ -102,7 +114,14 @@         <connect gate="G$1" pin="VCC" pad="5"/>         <connect gate="G$1" pin="Y" pad="4"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="SN74LVC1G332DBVR" constant="no"/>+          <attribute name="MANUFACTURER" value="Texas Instruments" constant="no"/>+          <attribute name="DIGIKEY_PN" value="296-18587-2-ND" constant="no"/>+          <attribute name="LCSC_PN" value="C43368" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>