← Commit history

Publish 0.2.0

Ray ·6f552e7257 · ·parent 9980361
3 files changed +26−12
README.md+14
@@ -40,6 +40,20 @@ SN74LVC1G332DBVR from Texas Instruments, in a SOT-23-6. Pinout and pin descripti - Footprint: `Package_TO_SOT_SMD:SOT-23-6` - 3D model: SOT-23-6 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`sn74lvc1g332dbvr.step`](sn74lvc1g332dbvr.step) | 97 KB | You want the bare part, or you mark your own boards. |+| [`sn74lvc1g332dbvr-etched.step`](sn74lvc1g332dbvr-etched.step) | 2.6 MB | You want the part with `SN74LVC1G332DBVR` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 653 faces against 117 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance  Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1
@@ -1,6 +1,6 @@ {   "slug": "sn74lvc1g332dbvr",-  "version": "0.1.0",+  "version": "0.2.0",   "type": "component",   "description": "Texas Instruments Gates, SOT-23-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "tags": [
page.json+11−11
@@ -4,7 +4,7 @@   "slug": "sn74lvc1g332dbvr",   "title": "SN74LVC1G332DBVR",   "brief": "Texas Instruments Gates, SOT-23-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.2.0",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -35,37 +35,37 @@         "number": "1",         "name": "A",         "type": "input",-        "description": "Logic input A of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. VIH = 0.7\u00d7VCC and VIL = 0.3\u00d7VCC at VCC = 4.5-5.5 V. Input leakage \u00b15 \u00b5A max."+        "description": "Logic input A of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. VIH = 0.7×VCC and VIL = 0.3×VCC at VCC = 4.5-5.5 V. Input leakage ±5 µA max."       },       {         "number": "2",         "name": "GND",         "type": "power_in",-        "description": "Ground reference for the device. Continuous current through GND rated \u00b1100 mA max."+        "description": "Ground reference for the device. Continuous current through GND rated ±100 mA max."       },       {         "number": "3",         "name": "B",         "type": "input",-        "description": "Logic input B of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. Input leakage \u00b15 \u00b5A max, Ci \u2248 3.5 pF at 3.3 V."+        "description": "Logic input B of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC. Input leakage ±5 µA max, Ci ≈ 3.5 pF at 3.3 V."       },       {         "number": "4",         "name": "Y",         "type": "output",-        "description": "OR-gate output, Y = A + B + C. Push-pull CMOS output rated \u00b124 mA at VCC = 3 V (\u00b132 mA at VCC = 4.5 V). VOH \u2248 VCC \u2212 0.1 V at IOH = \u2212100 \u00b5A."+        "description": "OR-gate output, Y = A + B + C. Push-pull CMOS output rated ±24 mA at VCC = 3 V (±32 mA at VCC = 4.5 V). VOH ≈ VCC − 0.1 V at IOH = −100 µA."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Supply voltage input. Operating range 1.65 V to 5.5 V; data-retention minimum 1.5 V. Quiescent supply current ICC \u2264 10 \u00b5A. Bypass with a local 0.1 \u00b5F ceramic capacitor to GND."+        "description": "Supply voltage input. Operating range 1.65 V to 5.5 V; data-retention minimum 1.5 V. Quiescent supply current ICC ≤ 10 µA. Bypass with a local 0.1 µF ceramic capacitor to GND."       },       {         "number": "6",         "name": "C",         "type": "input",-        "description": "Logic input C of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC (supports down-translation to VCC). Input leakage \u00b15 \u00b5A max."+        "description": "Logic input C of the 3-input OR gate. CMOS input, accepts 0 V to 5.5 V regardless of VCC (supports down-translation to VCC). Input leakage ±5 µA max."       }     ],     "provenance": {@@ -139,9 +139,9 @@     "docs/hero.png",     "docs/sn74lvc1g332dbvr-datasheet.pdf",     "viewers/symbol.html",-    "viewers/footprint.html"+    "viewers/footprint.html",+    "pads.json"   ],-  "visibility": {-    "public": true-  }+  "visibility": "public",+  "description": "Texas Instruments Gates, SOT-23-6. Datasheet-verified pinout, KiCad symbol/footprint/3D." }\ No newline at end of file