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sn74lvc1g08dbvr: factory component page (tier=lcsc)

Ray ·e11312e75f · ·parent dfa1dba
1 file changed +98−8
page.json+98−8
@@ -1,13 +1,108 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "sn74lvc1g08dbvr",+  "title": "SN74LVC1G08DBVR",+  "brief": "UMW Gates, SOT-23-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "UMW Gates, SOT-23-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "sn74lvc1g08dbvr"   ],+  "component": {+    "mpn": "SN74LVC1G08DBVR",+    "manufacturer": "UMW",+    "package": "SOT-23-5",+    "pin_count": 5,+    "category": "Logic",+    "subcategory": "Gates",+    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/a6760d575b85b9c327149b97c5535b85.pdf",+    "parts": {+      "symbol": "sn74lvc1g08dbvr.kicad_sym",+      "footprint": "sn74lvc1g08dbvr.kicad_mod",+      "model_3d": "sn74lvc1g08dbvr.glb",+      "model_3d_step": "sn74lvc1g08dbvr.step",+      "lbr": "sn74lvc1g08dbvr.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "A",+        "type": "input",+        "description": "Logic input A to the 2-input AND gate. CMOS input, VIH \u2265 0.7\u00b7VCC (VCC = 3-5.5 V), input leakage \u00b15 \u00b5A max, VI range 0-5.5 V."+      },+      {+        "number": "2",+        "name": "B",+        "type": "input",+        "description": "Logic input B to the 2-input AND gate. CMOS input with the same VIH/VIL thresholds and \u00b15 \u00b5A leakage as input A."+      },+      {+        "number": "3",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference for the device. Continuous current through VCC or GND is limited to \u00b1100 mA."+      },+      {+        "number": "4",+        "name": "Y",+        "type": "output",+        "description": "AND-gate logic output (Y = A\u00b7B). Push-pull CMOS output rated \u00b132 mA at VCC = 4.5 V (VOH \u2265 3.8 V, VOL \u2264 0.55 V); propagation delay tPHL/tPLH \u2248 10 ns typ. with CL = 15 pF."+      },+      {+        "number": "5",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply voltage. Operating range 1.65 V to 5.5 V (abs. max 6.5 V); quiescent ICC \u2264 10 \u00b5A. Bypass with a 0.1 \u00b5F capacitor to GND close to the pin."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://datasheet.lcsc.com/datasheet/pdf/a6760d575b85b9c327149b97c5535b85.pdf",+        "pages": 15,+        "sha256": "d96a313b6463337a",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 5,+        "described": 5,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "UMW",+      "Package": "SOT-23-5",+      "Category": "Logic",+      "Pins": "5"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "sn74lvc1g08dbvr"+  ],+  "discovery_pitch": "SN74LVC1G08DBVR (UMW) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +120,5 @@     "docs/sn74lvc1g08dbvr-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file