SN74LVC1G08DBVR

@@ -42,6 +42,20 @@ SN74LVC1G08DBVR from Texas Instruments, in a SOT-23-5. Pinout and pin descriptio - Footprint: `Package_TO_SOT_SMD:SOT-23-5` - 3D model: SOT-23-5 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`sn74lvc1g08dbvr.step`](sn74lvc1g08dbvr.step) | 85 KB | You want the bare part, or you mark your own boards. |+| [`sn74lvc1g08dbvr-etched.step`](sn74lvc1g08dbvr-etched.step) | 2.4 MB | You want the part with `SN74LVC1G08DBVR` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 602 faces against 102 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance  Data extracted from the manufacturer datasheet, not a distributor listing:

@@ -1,6 +1,6 @@ {   "slug": "sn74lvc1g08dbvr",-  "version": "0.1.0",+  "version": "0.2.0",   "type": "component",   "description": "UMW Gates, SOT-23-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "tags": [

@@ -4,7 +4,7 @@   "slug": "sn74lvc1g08dbvr",   "title": "SN74LVC1G08DBVR",   "brief": "Texas Instruments Gates, SOT-23-5. Datasheet-verified pinout, KiCad symbol/footprint/3D.",-  "version": "0.1.0",+  "version": "0.2.0",   "license": "CC-BY-SA-4.0",   "tags": [     "component",@@ -34,31 +34,31 @@         "number": "1",         "name": "A",         "type": "input",-        "description": "Logic input A to the 2-input AND gate. CMOS input, VIH \u2265 0.7\u00b7VCC (VCC = 3-5.5 V), input leakage \u00b15 \u00b5A max, VI range 0-5.5 V."+        "description": "Logic input A to the 2-input AND gate. CMOS input, VIH ≥ 0.7·VCC (VCC = 3-5.5 V), input leakage ±5 µA max, VI range 0-5.5 V."       },       {         "number": "2",         "name": "B",         "type": "input",-        "description": "Logic input B to the 2-input AND gate. CMOS input with the same VIH/VIL thresholds and \u00b15 \u00b5A leakage as input A."+        "description": "Logic input B to the 2-input AND gate. CMOS input with the same VIH/VIL thresholds and ±5 µA leakage as input A."       },       {         "number": "3",         "name": "GND",         "type": "power_in",-        "description": "Ground reference for the device. Continuous current through VCC or GND is limited to \u00b1100 mA."+        "description": "Ground reference for the device. Continuous current through VCC or GND is limited to ±100 mA."       },       {         "number": "4",         "name": "Y",         "type": "output",-        "description": "AND-gate logic output (Y = A\u00b7B). Push-pull CMOS output rated \u00b132 mA at VCC = 4.5 V (VOH \u2265 3.8 V, VOL \u2264 0.55 V); propagation delay tPHL/tPLH \u2248 10 ns typ. with CL = 15 pF."+        "description": "AND-gate logic output (Y = A·B). Push-pull CMOS output rated ±32 mA at VCC = 4.5 V (VOH ≥ 3.8 V, VOL ≤ 0.55 V); propagation delay tPHL/tPLH ≈ 10 ns typ. with CL = 15 pF."       },       {         "number": "5",         "name": "VCC",         "type": "power_in",-        "description": "Positive supply voltage. Operating range 1.65 V to 5.5 V (abs. max 6.5 V); quiescent ICC \u2264 10 \u00b5A. Bypass with a 0.1 \u00b5F capacitor to GND close to the pin."+        "description": "Positive supply voltage. Operating range 1.65 V to 5.5 V (abs. max 6.5 V); quiescent ICC ≤ 10 µA. Bypass with a 0.1 µF capacitor to GND close to the pin."       }     ],     "provenance": {@@ -132,9 +132,9 @@     "docs/hero.png",     "docs/sn74lvc1g08dbvr-datasheet.pdf",     "viewers/symbol.html",-    "viewers/footprint.html"+    "viewers/footprint.html",+    "pads.json"   ],-  "visibility": {-    "public": true-  }+  "visibility": "public",+  "description": "UMW Gates, SOT-23-5. Datasheet-verified pinout, KiCad symbol/footprint/3D." }\ No newline at end of file